YSS902 Datasheet, PDF (6/12 Pages) YAMAHA CORPORATION – Dolby Digital (AC-3) / Pro Logic decoder + Sub DSP

YSS902
FUNCTION DESCRIPTION
The YSS902 consist of Main DSP section where AC-3/Pro Logic decoding is executed and Sub DSP section
where various sound field effects are added. Please refer to “BLOCK DIAGRAM” section.
Sub DSP is a 6 ch input / 6 ch output programmable DSP exclusively for the sound field processing. It can apply
such effects as virtual surround, echo and equalizing. In addition, with an SRAM up to 1Mbit connected, it can
produce reverberation for one second or longer. By using this function, it is possible to simulate various sound
fields such as a hall or a church.
* If adopting some technology owned by another company is desired for use in Sub DSP section, note that a
separate contract may be required between the owner of that technology and the user with respect to adoption of the
technology.
1. Clocks
XI, XO, CPO
The crystal oscillation circuit is formed by using XI and XO terminals. Oscillation frequency 50MHz is divided by
2 internally to provide the operating clock signals of 25MHz.
Clock signals should be obtained through self oscillation by using XI and XO terminals, or external clock signals
should be fed through the XI terminal.
This LSI operates in a PLL oscillation mode as well. When the PLL oscillation mode is selected and an external
clock signal whose frequency is lower than 49MHz is fed through the XI terminal and multiplied, connect an
external analog filter between CPO terminal and Ground.
2. Data Interface
SDIA0, SDIA1, SDOA0-2, SDIB0-2, SDOB0-2, SDWCK0, SDBCK0, SDWCK1,
SDBCK1, /SDBCK0
Main DSP section
AC-3 bitstream or PCM data should be fed from SDIA0 or SDIA1 terminal. These signals are processed by AC-3
/ Pro Logic decoding procedure in Main DSP section and then transmitted to Sub DSP section as well as
outputted through SDOA0-2 terminals.
Sub DSP section
In Sub DSP section, various types of processing can be applied to the PCM data decoded in Main DSP section or
inputted through SDIB0-2 terminals. Then, processed signals are outputted from each of SDOB0-2 terminals.
Following parameters can be selected by changing the control register setting.
. _{Selection of Main DSP input signal (SDIA0, SDIA1)}
. _{Selection of Sub DSP input signal (Main DSP output, SDIB0-2 input)}
. _{Polarity of bit clock and word clock}
. _{Format and bit count of input/output data}
For more information on the format of the input/output data, please refer to “Serial Data Interface” section.
3. Microprocessor Interface
/CS, /CSB, SCK, SI, SO
The control registers can be read/written via the serial microprocessor interface by using /CS, SCK, SI, and SO
terminals.
Please refer to the following format diagram for the details of read/write timing.
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