YMF795 Datasheet, PDF (27/45 Pages) YAMAHA CORPORATION – APL-2 Automobile sound Player-2

YMF795
Description of each state
Digital Power ON Ready
This is a state before turning on the digital power supply.
Hardware Reset
Input the hardware reset to the LSI in conjunction with the power-on of the digital power supply.
Analog Power ON Ready
This is a state before turning on the analog power supply. Turn on the analog power supply after the
initialization of the digital section.
Analog Power Down mode
This is a state in which power consumption of the analog section is the minimum.
Operation state is shifted to this operation mode after the analog power supply is turned on. In order to proceed
to the next step “Initialized” state, follow the procedure described on page 22.
Be sure to shift from the “Initialized” state in order to shift to this operation mode from a state except Analog
Power ON. (That is, each volume must be set to “MUITE.”)
A point to power down can be selected according to the usage. For details, refer to the description of
Power-down on pages of 21, 22, and 23. Be sure to power off the analog power supply from this state.
Initialized
This state is given after the Power Down mode of the analog and the digital section.
And, shift to the power-down mode from this state.
STOP
This is a state in which volume mute cancellation and the timbre data setting has been completed. In this state,
the FIFO is empty. This state returns when the melody reproduction is stopped.
And, transition to the power-down of the digital section is possible from this state. This state will return when
the power-down is cancelled.
PLAY Standby
This is a state that is given immediately before the playback of a piece after the write of musical score data into
FIFO. Setting bit ST to “1” will shift to the next “PLAY” state. Transition to the power-down of the digital
section is possible from this state. However, the state will return to “STOP” state after the power-down
cancellation.
PLAY
This is a state in which a piece is being played back. Setting bit ST to “0” will shift to the “STOP” state.
Transition to the power-down of the digital section from this state is prohibited. (Noise may be generated.)
Digital Power Down mode
This is a state in which the digital section is in the power-down state. (DP bit = “1”)
This state can reduce the power consumption of the digital section because a clock is not input to the LSI even
if it is input to CLK_I pin. Make the HP Volume and FM Volume mute state before shifting to this mode.
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