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YMU757B Datasheet, PDF (21/43 Pages) YAMAHA CORPORATION – MA-1C
YMU757B
Power-down control division diagram
As for the power-down, it is possible to divide an inside function separately and to control it.
The power-down is controlled by Index 38h.
Controlled by
using DP bit
Controlled by
using AP4 bit
Controlled by
using AP2 bit
SCLK
SYNC
SDIN
Serial
I/F
/IRQ
/RST
Timing Generator
Register
RAM
FIFO
16b x 32w
FM
Synthesizer
4 sounds
generated
simultaneously
VOL
32step
DAC
VREF
Controlled by
using AP1 bit
VREF
VOL
32step
EQ
VOL
32step
AMP
EQ1
EQ2
EQ3
SPOUT
SPOUT
SPVSS
Controlled by
using AP3 bit
Explanation of each bit
DP
It is the bit to make the power-down whole of the digital department.
Because clock to move inside stops consumption electric current of the digital part can be restrained in minimum.
Data on FIFO are cleared though contents of a register are held.
AP1
It is the bit that the power-down a VREF circuit decline.
If AP1 is set to “1”, the whole of the analog part stops. Because an analog center voltage is made by VREF circuit.
AP2
It is the bit to make power-down FM volume part, EQ circuit, speaker volume, and non-reversal amplifier side of
speaker output part.
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