XC9536XV Datasheet, PDF (8/8 Pages) Xilinx, Inc – 36 macrocells with 800 usable gates

XC9536XV High-performance CPLD
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Revision History
Date
02/01/00
01/29/01
05/15/01
08/27/01
05/31/02
05/27/03
08/21/03
04/15/05
Revision No.
Description
1.1
Initial Xilinx release. Advance information specification.
2.0
Added -3 performance specification and VQ44 package. Deleted VQ64 package.
Updated I_CC vs. Frequency Figure 1.
2.1
Updated I_CC formula, Recommended Operation Conditions, -3, -4, and -5 AC
Characteristics and Internal Timing Parameters
2.2
Changed V_CCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: I_IL
- added "low" current, I_IH - changed to "Input leakage high current"; Internal Timing: -3
T_CGK from 0.3 to 0.8; -5 T_AOI from 6.5 to 5.9.
2.3
Updated I_CC equation on page 1. Removed -3 device. Changed to Preliminary. Added
C4 and D4 as NCs in the CS48 package pinouts. Added second test condition and max
measurement to I_IH DC Characteristics. Added Part Marking Information to Ordering
Information. Removed -4 device.
2.4
Updated T_SOL from 260 to 220^oC. Updated Device Part Marking.
2.5
Updated Package Device Marking Pin 1 orientation.
2.6
Added T_APRPW specification to AC Characteristics. Added IOSTANDARD information.
8
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DS053 (v2.6) April 15, 2005
Product Specification