XC9536XV Datasheet, PDF (1/8 Pages) Xilinx, Inc – 36 macrocells with 800 usable gates

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XC9536XV High-performance
CPLD
DS053 (v2.6) April 15, 2005
0 1 _{Product Specification}
Features
• 36 macrocells with 800 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (36 user I/O pins)
• Optimized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 3.3V-core XC9536XL device in the
44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages
Description
The XC9536XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of two
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I_CC, the following equation may be
used:
P_TOTAL = P_INT + P_IO = I_CCINT x V_CCINT + P_IO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. P_IO is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. I_CCINT is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
I_CCINT (taken from simulation) is:
I_CCINT(mA) = MC_HS(0.122 X PT_HS + 0.238) + MC_LP(0.042 x
PT_LP + 0.171) + 0.04(MC_HS + MC_LP) x f_MAX x MC_TOG
where:
MC_HS = # macrocells used in high speed mode
MC_LP = #macrocells used in low power mode
PT_HS = average p-terms used per high speed macrocell
PT_LP = average p-terms used over low power macrocell
f_MAX = max clocking frequency in the device
MC_TOG = % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I_CC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP361, “Planning for High Speed
XC9500XV Designs.”
60
200 MHz
50
40
30
20
High ^Performance
Low ^Power
120 MHz
10
0
50
100
150
200
Clock Frequency (MHz)
DS053_01_121501
Figure 1: Typical I_CC vs. Frequency for XC9536XV
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DS053 (v2.6) April 15, 2005
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Product Specification