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XA2C64A-8VQG44Q Datasheet, PDF (6/16 Pages) Xilinx, Inc – Guaranteed to meet full electrical specifications over
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XA2C64A CoolRunner-II Automotive CPLD
R
AC Electrical Characteristics Over Recommended Operating Conditions
-7
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Symbol
Parameter
Min. Max. Min. Max. Units
TPD1
Propagation delay single p-term
-
6.7
-
6.7 ns
TPD2
Propagation delay OR array
-
7.5
-
7.5 ns
TSUD
Direct input register clock setup time
3.3
-
3.3
-
ns
TSU1
Setup time (single p-term)
2.5
-
2.8
-
ns
TSU2
Setup time (OR array)
3.3
-
3.6
-
ns
THD
Direct input register hold time
0.0
-
0.0
-
ns
TH
P-term hold time
0.0
-
0.0
-
ns
TCO
Clock to output
-
6.0
-
6.0 ns
FTOGGLE(1)
Internal toggle rate(1)
-
300
-
300 MHz
FSYSTEM1(2) Maximum system frequency(2)
-
159
-
152 MHz
FSYSTEM2(2) Maximum system frequency(2)
-
141
-
135 MHz
FEXT1(3)
Maximum external frequency(3)
-
118
-
114 MHz
FEXT2(3)
Maximum external frequency(3)
-
108
-
104 MHz
TPSUD
Direct input register p-term clock setup time
1.7
-
1.7
-
ns
TPSU1
P-term clock setup time (single p-term)
0.9
-
0.9
-
ns
TPSU2
P-term clock setup time (OR array)
1.7
-
1.7
-
ns
TPHD
Direct input register p-term clock hold time
1.4
-
1.4
-
ns
TPH
P-term clock hold
2.7
-
2.7
-
ns
TPCO
P-term clock to output
-
8.4
-
8.4 ns
TOE/TOD
Global OE to output enable/disable
-
10.0
-
10.0 ns
TPOE/TPOD
P-term OE to output enable/disable
-
11.0
-
11.0 ns
TMOE/TMOD Macrocell driven OE to output enable/disable
-
11.0
-
11.0 ns
TPAO
P-term set/reset to output valid
-
9.7
-
9.7
ns
TAO
Global set/reset to output valid
-
8.3
-
8.3 ns
TSUEC
Register clock enable setup time
3.7
-
3.7
-
ns
THEC
Register clock enable hold time
0.0
-
0.0
-
ns
TCW
Global clock pulse width High or Low
2.2
-
2.2
-
ns
TPCW
P-term pulse width High or Low
7.5
-
7.5
-
ns
TAPRPW
Asynchronous preset/reset pulse width (High or Low)
7.5
-
7.5
-
ns
TCONFIG(4)
Configuration time
-
50.0
-
50
μs
Notes:
1. FTOGGLE is the maximum frequency of a dual edge triggered T flip-flop with output enabled.
2. FSYSTEM (1/TCYCLE) is the internal operating frequency for a device fully populated with 16-bit up/down, Resetable binary counter
(one counter per function block).
3. FEXT (1/TSU1+TCO) is the maximum external frequency.
4. Typical configuration current during TCONFIG is 2.3 mA.
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DS553 (v1.1) May 5, 2007
Product Specification
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