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DS556 Datasheet, PDF (6/19 Pages) Xilinx, Inc – Available in the following package option
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XA2C384 CoolRunner-II Automotive CPLD
R
AC Electrical Characteristics Over Recommended Operating Conditions
-10
-11
Symbol
Parameter
Min. Max. Min. Max. Units
TPD1
Propagation delay single p-term
-
9.2
-
9.2
ns
TPD2
Propagation delay OR array
-
10.0
-
10.0 ns
TSUD
Direct input register set-up time
4.2
-
4.5
-
ns
TSU1
Setup time fast (single p-term)
3.3
-
3.8
-
ns
TSU2
Setup time (OR array)
4.1
-
4.6
-
ns
THD
Direct input register hold time
0.0
-
0.0
-
ns
TH
Hold time (OR array or p-term)
0.0
-
0.3
-
ns
TCO
FTOGGLE(1)
Clock to output
Internal toggle rate
-
7.9
-
7.9 ns
-
166
-
166 MHz
FSYSTEM1(2) Maximum system frequency
-
125
-
118 MHz
FSYSTEM2(2) Maximum system frequency
-
114
-
108 MHz
FEXT1(3)
Maximum external frequency
-
89
-
85 MHz
FEXT2(3)
Maximum external frequency
-
83
-
80 MHz
TPSUD
Direct input register p-term clock setup time
2.5
-
2.7
-
ns
TPSU1
P-term clock setup time (single p-term)
1.9
-
2.1
-
ns
TPSU2
P-term clock setup time (OR array)
2.7
-
2.9
-
ns
TPHD
Direct input register p-term clock hold time
0.4
-
1.2
-
ns
TPH
P-term clock hold
1.3
-
1.7
-
ns
TPCO
P-term clock to output
-
9.3
-
9.3
ns
TOE/TOD
Global OE to output enable/disable
-
9.2
-
9.2
ns
TPOE/TPOD
P-term OE to output enable/disable
-
10.2
-
10.4 ns
TMOE/TMOD Macrocell driven OE to output enable/disable
-
12.5
-
12.5 ns
TPAO
P-term set/reset to output valid
-
11.6
-
11.6 ns
TAO
Global set/reset to output valid
-
11.5
-
11.5 ns
TSUEC
Register clock enable setup time
3.4
-
4.0
-
ns
THEC
Register clock enable hold time
0.0
-
0.3
-
ns
TCW
Global clock pulse width High or Low
3.0
-
3.0
-
ns
TPCW
P-term pulse width High or Low
10.0
-
10.0
-
ns
TAPRPW
Asynchronous preset/reset pulse width (High or Low)
10.0
-
10.0
-
ns
TDGSU
Set-up before DataGATE latch assertion
0.0
-
0.0
-
ns
TDGH
Hold to DataGATE latch assertion
6.0
-
6.0
-
ns
TDGR
DataGATE recovery to new data
11.0
11.0 ns
TDGW
DataGATE low pulse width
5.0
-
5.0
-
ns
TCDRSU
CDRST setup time before falling edge GCLK2
2.5
-
2.5
-
ns
TCDRH
CDRST hold time before falling edge GCLK2
0.0
-
0.2
-
ns
TCONFIG
Configuration time
-
200
-
200 μs
Notes:
1. FTOGGLE is the maximum frequency of a T flip-flop can reliably toggle (see CoolRunner-II Automotive CPLD family data sheet).
2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device with 16-bit Resetable binary counter through one p-term per
macrocell while FSYSTEM2 is through the OR array (one counter per function block)
3. FEXT1(1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array
4. Typical configuration current during TCONFIG is 25 mA.
6
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DS556 (v1.1) May 5, 2007
Product Specification
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