DS556 Datasheet, PDF (15/19 Pages) Xilinx, Inc – Available in the following package option

R
Pin Descriptions (Continued)
Function Block
23
Macrocell
1
TQG144
-
23
2
-
23
3
85
23
4
86
23
5
87
23
6
-
23
7
-
23
8
-
23
9
-
23
10
-
23
11
-
23
12
88
23
13
91
23
14
92
23
15
-
23
16
-
I/O Bank
3
3
3
3
3
-
-
-
-
-
-
3
3
3
3
3
XA2C384 CoolRunner-II Automotive CPLD
Pin Descriptions (Continued)
Function Block
24
Macrocell
1
TQG144
-
I/O Bank
3
24
2
58
3
24
3
-
3
24
4
-
3
24
5
-
3
24
6
-
-
24
7
-
-
24
8
-
-
24
9
-
-
24
10
-
-
24
11
-
-
24
12
57
3
24
13
-
3
24
14
56
3
24
15
-
3
24
16
-
3
Notes:
1. GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
2. GCK, GSR, and GTS pins can also be used for general
purpose I/O.
XA2C384 JTAG, Power/Ground, No Connect Pins and Total User I/O
Pin Type
TQG144
TCK
67
TDI
63
TDO
122
TMS
65
V_CCAUX (JTAG supply voltage)
Power internal (V_CC)
Power Bank 1 I/O (V_CCIO1)
Power Bank 2 I/O (V_CCIO2)
Power Bank 3 I/O (V_CCIO3)
Power Bank 4 I/O (V_CCIO4)
Ground
8
1, 37, 84
27, 55
141
73, 93
109, 127
29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144
No connects
-
Total user I/O (includes dual function pins)
118
DS556 (v1.1) May 5, 2007
www.xilinx.com
15
Product Specification