DS205 Datasheet, PDF (6/12 Pages) Xilinx, Inc – LogiCORE IP 64-Bit

LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI
as look-up tables and segmented routing. Also included is floor planning information, such as logic mapping and
location constraints. This technology provides the best physical layout, predictability, and performance. In
addition, these features allow for significantly reduced compile times over competing architectures.
To guarantee the critical setup, hold, minimum clock-to-out, and maximum clock-to-out timing, the core is
delivered with Smart-IP constraint files that are unique for a device and package combination. These constraints
files guide the implementation tools so that the critical paths always are within specification.
Xilinx provides Smart-IP constraints files for many device and package combinations. Constraints files for
unsupported device and package combinations can be generated using the web-based constraints file generator.
Functional Description
Figure 1 illustrates the Initiator/Target core for PCI partitioned into five major blocks and a user application.
X-Ref Target - Figure 1
PAR
PAR64
PERR-
SERR-
Parity
Generator/
Checker
Base
Address
Register
0
Base
Address
Register
1
Base
Address
Register
2
Command/
Status
Register
AD[63:0]
ADIO[63:0]
FRAME-
IRDY-
REQ-
GNT-
REQ64-
Initiator
State
Machine
Interrupt
Pin and
Line
Register
Latency
Timer
Register
PCI Configuration Space
Vendor ID,
Rev ID,
Other User
Data
ACK64-
TRDY-
DEVSEL-
STOP-
Target
State
Machine
Figure 1: Block Diagram of the Initiator/Target Core for PCI
I/O Interface Block for PCI
The I/O interface block handles the physical connection to the PCI bus including all signaling, input and output
synchronization, output 3-state controls, and all request-grant handshaking for bus mastering.
User Application
The Initiator/Target core for PCI provides a simple, general-purpose interface for a wide range of applications.
DS205 October 16, 2012
www.xilinx.com
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Product Specification v3.167 & v4.18