XCS40 Datasheet, PDF (59/82 Pages) Xilinx, Inc – Spartan and Spartan-XL Families Field Programmable Gate Arrays

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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading.
Spartan-XL Setup and Hold
Speed Grade
-5
-4
Symbol
Description
Device
Max
Max
Units
Input Setup/Hold Times Using Global Clock and IFF
T_SUF/T_HF No Delay
XCS05XL 1.1/2.0
1.6/2.6
ns
XCS10XL 1.0/2.2
1.5/2.8
ns
XCS20XL 0.9/2.4
1.4/3.0
ns
XCS30XL 0.8/2.6
1.3/3.2
ns
XCS40XL 0.7/2.8
1.2/3.4
ns
T_SU/T_H
Full Delay
XCS05XL 3.9/0.0
5.1/0.0
ns
XCS10XL 4.1/0.0
5.3/0.0
ns
XCS20XL 4.3/0.0
5.5/0.0
ns
XCS30XL 4.5/0.0
5.7/0.0
ns
XCS40XL 4.7/0.0
5.9/0.0
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
Capacitive Load Factor
Figure 35 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified
3
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2
2.5 ns to the specified delay. If the load capacitance is 20
pF, subtract 0.8 ns from the specified output delay.
Figure 35 is usable over the specified operating conditions
1
of voltage and temperature and is independent of the output
slew rate control.
0
-1
-2
0
20 40 60 80 100 120 140
Capacitance (pF)
DS060_35_080400
Figure 35: Delay Factor at Various Capacitive Loads
DS060 (v1.6) September 19, 2001
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Product Specification
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