XCS40 Datasheet, PDF (23/82 Pages) Xilinx, Inc – Spartan and Spartan-XL Families Field Programmable Gate Arrays

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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 12: Boundary Scan Instructions
Instruction
I2 I1 I0
Test
Selected
TDO
Source
000
EXTEST
DR
001
SAMPLE/
DR
PRELOAD
010
USER 1
BSCAN.
TDO1
011
USER 2
BSCAN.
TDO2
1 0 0 READBACK Readback
Data
1 0 1 CONFIGURE
DOUT
110
IDCODE
IDCODE
(Spartan-XL Register
only)
111
BYPASS
Bypass
Register
I/O Data
Source
DR
Pin/Logic
User Logic
User Logic
Pin/Logic
Disabled
-
-
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-state. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 21.
The device-specific pinout tables for the Spartan/XL devices
include the boundary scan locations for each IOB pin.
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MODE.I
(TDI end)
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
DS060_21_080400
Figure 21: Boundary Scan Bit Sequence
BSDL (Boundary Scan Description Language) files for
Spartan/XL devices are available on the Xilinx website in
the File Download area. Note that the 5V Spartan devices
and 3V Spartan-XL devices have different BSDL files.
Including Boundary Scan in a Design
If boundary scan is only to be used during configuration, no
special schematic elements need be included in the sche-
matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func-
tions after configuration.
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 22.
Optional
IBUF
To User
Logic
TDI
TMS
TCK
From
User Logic
BSCAN
TDI
TDO
TMS
DRCK
TCK
IDLE
TDO1
SEL1
TDO2
SEL2
TDO
To User
Logic
DS060_22_080400
Figure 22: Boundary Scan Schematic Example
DS060 (v1.6) September 19, 2001
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