DS879 Datasheet, PDF (5/7 Pages) Xilinx, Inc – Video Remapper v1.00a

Video Remapper v1.00a
AXI4-Stream Signal Names and Descriptions
Table 3 describes the AXI4-Stream inbound signal names and descriptions.
Table 3: AXI4-Stream Data Interface Signal Descriptions
Signal Name
Direction
Width
s_axis_tdata
Automatically calculated based on
In
C_NUM_S_COMPONENTS and
C_S_AXIS_COMPONENT_WIDTH
s_axis_tvalid
In
1
s_axis_tready
Out
1
s_axis_tuser
In
1
s_axis_tlast
In
1
Table 4 describes the AXI4-Stream outbound signal names and descriptions.
Table 4: AXI4-Stream Data Interface Signal Descriptions
Signal Name
Direction
Width
m_axis_tdata
Automatically calculated based on
Out
C_NUM_M_COMPONENTS and
C_M_AXIS_COMPONENT_WIDTH
m_axis_tvalid
Out
1
m_axis_tready
In
1
m_axis_tuser
Out
1
m_axis_tlast
Out
1
Description
Input Video Data
Input Video Valid Signal
Input Ready
Input Video Start Of Frame
Input Video End Of Line
Description
Interface Output Video Data
Interface Output Video Valid
Interface Output Video Ready
Interface Output Video Start of
Frame
Interface Output Video End of
Line
Video Data
The AXI4-Stream interface specification restricts TDATA widths to integer multiples of 8 bits. The Video Remapper
*_axis_tdata is packed and padded to multiples of 8 bits as necessary. Zero padding the most significant bits is
only necessary for 10 and 12 bit wide data.
Component Data Widths
If the outbound component data width (C_M_COMPONENT_WIDTH) is greater than the inbound component data
width (C_S_COMPONENT_WIDTH), then the outbound component data is zero padded on the least significant bits.
If the outbound component data width (C_M_COMPONENT_WIDTH) is less than the inbound component data width
(C_S_COMPONENT_WIDTH), then the outbound component data is truncated on the least significant bits.
READY/VALID Handshake
A valid transfer occurs whenever READY, VALID, and aresetn are high at the rising edge of aclk, as seen in
Figure 3. During valid transfers, DATA only carries active video data. Blank periods and ancillary data packets are
not transferred through the AXI4-Stream video protocol.
DS879 October 16, 2012
www.xilinx.com
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Product Specification