DS879 Datasheet, PDF (4/7 Pages) Xilinx, Inc – Video Remapper v1.00a

Video Remapper v1.00a
Core Interfaces
Port Descriptions
The Video Remapper core is compliant with the AXI4-Stream Video Protocol standard. Figure 2 illustrates an I/O
diagram of the Video Remapper core.
X-Ref Target - Figure 2
AXIS?VREMAPPER
!8) 3TREAM
3LAVEINBOUND
INTERFACE
S?AXIS?TVALID
S?AXIS?TDATA
S?AXIS?TLAST
S?AXIS?TUSER
S?AXIS?TREADY
M?AXIS?TVALID
M?AXIS?TDATA
M?AXIS?TLAST
M?AXIS?TUSER
M?AXIS?TREADY
!8) 3TREAM
-ASTEROUTBOUND
INTERFACE
#ORE#LOCK
AND2ESET
ACLK
ARESETN
8
Figure 2: Video Remapper Core Top-Level Signaling Interface
Common Interface Signals
Table 2 summarizes the signals which are either shared by, or not part of the dedicated AXI4-Stream data control
interfaces.
Table 2: Common Interface Signals
Signal Name Direction Width
Description
aclk
In
1 Video Core Clock
aresetn
In
1 Video Core Active Low Synchronous Reset
The aclk and aresetn signals are shared between the core and the AXI4-Stream data interfaces.
aclk
The AXI4-Stream interface must be synchronous to the core clock signal aclk. All AXI4-Stream interface’s input
signals are sampled on the rising edge of aclk. All AXI4-Stream output signal’s changes occur after the rising edge
of aclk.
aresetn
The aresetn signal must be synchronous to the aclk and must be held low for a minimum of 32 clock cycles of the
slowest clock.
Data Interface
The Video Remapper core receives and transmits data using AXI4-Stream interfaces that implement a video
protocol as defined in the Video IP: AXI Feature Adoption section of the (UG761) AXI Reference Guide [Ref 1].
DS879 October 16, 2012
www.xilinx.com
4
Product Specification