XQVR300 Datasheet, PDF (4/14 Pages) Xilinx, Inc – QPro Virtex 2.5V Radiation

QPro Virtex 2.5V Radiation Hardened FPGAs
R
QPro Virtex Pinouts
Device/Package Combinations and Maximum I/O
Package
CB228
CG560
Maximum User I/O (excluding dedicated clock pins)
XQVR300
XQVR600
XQVR1000
162
162
-
-
-
404
Pinout Tables
See the Xilinx WebLINX web site (http://www.xil-
inx.com/partinfo/databook.htm) for updates or additional
pinout information. For convenience, Table 2 and Table 3 list
the locations of special-purpose and power-supply pins.
Pins not listed are user I/Os.
Table 2: Virtex Ceramic Column Grid (CG560) Pinout
Pin Name
GCK0
GCK1
GCK2
GCK3
M0
M1
M2
CCLK
PROGRAM
DONE
INIT
BUSY/DOUT
D0/DIN
D1
D2
D3
D4
D5
D6
D7
WRITE
CS
TDI
Device
XQVR1000
CG560
AL17
AJ17
D17
A17
AJ29
AK30
AN32
C4
AM1
AJ5
AH5
D4
E4
K3
L4
P3
W4
AB5
AC4
AJ4
D6
A2
D5
Table 2: Virtex Ceramic Column Grid (CG560) Pinout
(Continued)
Pin Name
Device
CG560
TDO
XQVR1000
E6
TMS
B33
TCK
E29
DXN
AK29
DXP
AJ28
V_CCINT
(V_CCINT pins are listed
incrementally. Connect
all pins listed for both the
required device and all
smaller devices listed in
the same package.)
A21, B12,
B14, B18,
B28, C22,
C24, E9,
E12, F2,
H30, J1,
K32, M3,
N1, N29,
N33, U5,
U30, Y2,
Y31, AB2,
AB32, AD2,
AD32, AG3,
AG31, AJ13,
AK8, AK11,
AK17, AK20,
AL14, AL22,
AL27, AN25
V_CCO, Bank 0
A22, A26,
A30, B19, B32
V_CCO, Bank 1
A10, A16,
B13, C3, E5
V_CCO, Bank 2
B2, D1,
H1, M1, R2
4
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DS028 (v1.2) November 5, 2001
1-800-255-7778
Preliminary Product Specification