XQVR300 Datasheet, PDF (10/14 Pages) Xilinx, Inc – QPro Virtex 2.5V Radiation

QPro Virtex 2.5V Radiation Hardened FPGAs
Table 3: CQFP Package (CB228) (Continued)
Function
Pin #
Bank #
GND
1, 8, 14, 27, 42,
-
48, 56, 66, 72,
86, 100, 106,
113, 123, 129,
143, 157, 163,
173, 180, 186,
200, 215, 221
V_CCINT
15, 30, 41, 73,
-
83, 99, 130,
140, 156, 187,
203, 214
V_CCO
18, 28, 37, 58,
-
76, 85, 95, 115,
133, 142, 152,
171, 191, 201,
210, 228
Pinout Diagrams
The following diagrams illustrate the locations of spe-
cial-purpose pins on Virtex FPGAs. Table 4 lists the sym-
bols used in these diagrams. The diagrams also show
I/O-bank boundaries.
Table 4: Pinout Diagram Symbols
Symbol
Pin Function
S
General I/O
d
Device-dependent general I/O, n/c on
smaller devices
V
V_CCINT
R
Table 4: Pinout Diagram Symbols (Continued)
Symbol
Pin Function
v
Device-dependent V_CCINT, n/c on smaller
devices
O
V_CCO
R
V_REF
r
Device-dependent V_REF, remains I/O on
smaller devices
G
Ground
Ø, 1, 2, 3 Global Clocks
❿, ❶, ❷ M0, M1, M2
➉, ➀, ➁, ➂, D0/DIN, D1, D2, D3, D4, D5, D6, D7
➃, ➄, ➅, ➆
B
DOUT/BUSY
D
DONE
P
PROGRAM
I
INIT
K
CCLK
W
WRITE
S
CS
T
Boundary-scan test access port
+
Temperature diode, anode
–
Temperature diode, cathode
n
No connect
10
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Preliminary Product Specification