DS647 Datasheet, PDF (4/5 Pages) Xilinx, Inc – LogiCORE IP Utility Differential

LogiCORE IP Utility Differential Signaling Buffer (v1.01a)
Device Utilization and Performance Benchmarks
Table 4: Utility Differential Signaling Buffer Resource Utilization
Parameter
Resources
IBUFDS IBUFGDS OBUFDS IOBUFDS IBUFDSGTXE IBUFDSGTE
C_BUF_TYPE=IBUFDS
n
0
0
0
0
0
C_BUF_TYPE=IBUFGDS
0
n
0
0
0
0
C_BUF_TYPE=OBUFDS
0
0
n
0
0
0
C_SIZE=n
C_BUF_TYPE=IOBUFDS
0
0
0
n
0
0
C_BUF_TYPE=IBUFDSGTXE
0
0
0
0
n
0
C_BUF_TYPE=IBUFDSGTE
0
0
0
0
0
n
Support
Xilinx provides technical support for this LogiCORE™ IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE^® Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx Integrated
Software Environment (ISE^®) Embedded Edition software (EDK). For more information, visit the Utility
Differential Signaling Buffer product page.
Contact your local Xilinx sales representative for pricing and availability of additional Xilinx LogiCORE IP modules
and software. Information about additional Xilinx LogiCORE IP modules is available on the Xilinx IP Center.
Revision History
The following table shows the revision history for this document:
Date
9/25/07
7/25/08
9/16/09
01/18/12
Version
1.0
1.2
1.3
1.4
Description of Revisions
Initial Xilinx release.
Added QPro Virtex-4 Hi-Rel and QPro Virtex-4 Rad Tolerant FPGA support.
Created v1.01a for EDK_L 11.3 release, incorporated CR530738.
GTXE support added. Xilinx release 13.4.
DS647 January 18, 2012
www.xilinx.com
4
Product Specification