DS647 Datasheet, PDF (3/5 Pages) Xilinx, Inc – LogiCORE IP Utility Differential

LogiCORE IP Utility Differential Signaling Buffer (v1.01a)
Parameter - Port Dependencies
The parameter and port dependencies are listed and described in Table 3.
Table 3: Utility Differential Signaling Buffer Parameters - Port Dependencies
Name Affects Depends
Relational Description
Design Parameters
C_SIZE All signals 0 to C_SIZE-1 Scale width of all port signals
Port Signals
IBUF_*
OBUF_*
All signals
C_BUF_TYPE
C_BUF_TYPE
Valid for C_BUF_TYPE=IBUFDS or IBUFGDS, or IBUFDSGTXE, or IBUFDSGTE
and not used for other cases
Valid for C_BUF_TYPE=OBUFDS, not used for other cases
IOBUF_*
C_BUF_TYPE Valid for C_BUF_TYPE=IOBUFDS, not used for other cases
Figure 2 shows three instantiation cases for the core.
X-Ref Target - Figure 2
IBUFDS or IBUFGDS
IBUF_DS_F
IBUF_DS_N
IBUF_OUT
This diagram shows the case where the
core instantiates input differential signaling
buffer(s) to bring in off-chip differential signals.
OBUFDS
OBUF_IN
OBUF_DS_F This diagram shows the case where
OBUF_DS_N the core instantiates output differential
signaling buffer(s) to bring out internal
signals as differential signal pairs.
IOBUFDS
IOBUF_IO_T
IOBUF_IO_I
IOBUF_IO_C
This diagram shows the case where
IOBUF_DS_F ^{the core instantiates three-state differential}
IOBUF_DS_N ^{signaling buffer(s) for three-state differential}
signaling I/Os.
Figure 2: Utility Vector Logic Block Diagram
DS647_02_012407
Design Implementation
Design Tools
The Utility Differential Signaling Buffer design is handwritten. Xilinx^® XST is the synthesis tool used for
synthesizing the core.
Target Technology
The target technology is the 7 Series, Zynq™-7000, Virtex^® and Spartan^® family FPGAs.
DS647 January 18, 2012
www.xilinx.com
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Product Specification