DS187 Datasheet, PDF (30/72 Pages) Xilinx, Inc – Zynq-7000 All Programmable SoC

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
Table 42: SPI Slave Mode Interface Switching Characteristics⁽¹⁾⁽²⁾
Symbol
Description
Min
Max
Units
T_SSPIDCK
Input setup time for SPI{0,1}_MOSI and SPI{0,1}_SS
1
T_SSPICKD
Input hold time for SPI{0,1}_MOSI and SPI{0,1}_SS
1
T_SSPICKO
Output delay for SPI{0,1}_MISO
0
T_SSPISSCLK
Slave select asserted to first active clock edge
1
T_SSPICLKSS
Last active clock edge to slave select deasserted
1
F_SSPICLK
SPI slave mode device clock frequency
–
F_{SPI_REF_CLK} SPI reference clock frequency
–
–
F_{SPI_REF_CLK} cycles
–
F_{SPI_REF_CLK} cycles
2.6
F_{SPI_REF_CLK} cycles
–
F_{SPI_REF_CLK} cycles
–
F_{SPI_REF_CLK} cycles
25
MHz
200
MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 14
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
T_SSPISSCLK
T_SSPICLKSS
T_SSPIDCK
T_SSPICKD
Dn
Dn–1
Dn
Dn–1
Dn–2
T_SSPICKO
Dn–2
Dn–3
Dn–3
D0
D0
Figure 14: SPI Slave (CPHA = 0) Interface Timing Diagram
DS187_12_021013
X-Ref Target - Figure 15
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
T_SSPISSCLK
T_SSPIDCK
T_SSPICKD
Dn
Dn–1
Dn
Dn–1
Dn–2
T_SSPICKO
Dn–2
Dn–3
Dn–3
Figure 15: SPI Slave (CPHA = 1) Interface Timing Diagram
T_SSPICLKSS
D0
D0
DS187_13_021013
DS187 (v1.19) October 3, 2016
Product Specification
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