DS187 Datasheet, PDF (19/72 Pages) Xilinx, Inc – Zynq-7000 All Programmable SoC

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
Table 28: DDR3L Interface Switching Characteristics (800 Mb/s)⁽¹⁾ (Cont’d)
Symbol
Description
Min
Max Units
T_CKCA(6)
Command/address output hold time with respect to CLK
853
–
ps
Notes:
1. Recommended V_{CCO_DDR} = 1.35V ±5%.
2. Measurement is taken from V_REF to V_REF.
3. Measurement is taken from either the rising edge of DQ that crosses V_IH(AC) or the falling edge of DQ that crosses V_IL(AC) to V_REF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V_IL(DC) or the falling edge of DQ that crosses V_IH(DC) to V_REF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V_IH(AC) or the falling edge of CMD/ADDR that crosses
V_IL(AC) to V_REF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V_IL(DC) or the falling edge of CMD/ADDR that crosses
V_IH(DC) to V_REF of CLK.
Table 29: LPDDR2 Interface Switching Characteristics (800 Mb/s)⁽¹⁾
Symbol
Description
Min
Max Units
T_DQVALID(2)
T_DQDS(3)
T_DQDH(4)
Input data valid window
Output DQ to DQS skew
Output DQS to DQ skew
500
–
ps
196
–
ps
328
–
ps
T_DQSS
T_CACK(5)
T_CKCA(6)
Output clock to DQS skew
Command/address output setup time with respect to CLK
Command/address output hold time with respect to CLK
0.90
202
353
1.06
T_CK
–
ps
–
ps
Notes:
1. Recommended V_{CCO_DDR} = 1.2V ±5%.
2. Measurement is taken from V_REF to V_REF.
3. Measurement is taken from either the rising edge of DQ that crosses V_IH(AC) or the falling edge of DQ that crosses V_IL(AC) to V_REF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V_IL(DC) or the falling edge of DQ that crosses V_IH(DC) to V_REF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V_IH(AC) or the falling edge of CMD/ADDR that crosses V_IL(AC)
to V_REF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V_IL(DC) or the falling edge of CMD/ADDR that crosses
V_IH(DC) to V_REF of CLK.
Table 30: LPDDR2 Interface Switching Characteristics (400 Mb/s)⁽¹⁾
Symbol
Description
Min
Max Units
T_DQVALID(2)
T_DQDS(3)
T_DQDH(4)
Input data valid window
Output DQ to DQS skew
Output DQS to DQ skew
500
–
ps
664
–
ps
766
–
ps
T_DQSS
T_CACK(5)
T_CKCA(6)
Output clock to DQS skew
Command/address output setup time with respect to CLK
Command/address output hold time with respect to CLK
0.90
731
907
1.06
T_CK
–
ps
–
ps
Notes:
1. Recommended V_{CCO_DDR} = 1.2V ±5%.
2. Measurement is taken from V_REF to V_REF.
3. Measurement is taken from either the rising edge of DQ that crosses V_IH(AC) or the falling edge of DQ that crosses V_IL(AC) to V_REF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V_IL(DC) or the falling edge of DQ that crosses V_IH(DC) to V_REF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V_IH(AC) or the falling edge of CMD/ADDR that crosses V_IL(AC)
to V_REF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V_IL(DC) or the falling edge of CMD/ADDR that crosses
V_IH(DC) to V_REF of CLK.
DS187 (v1.19) October 3, 2016
Product Specification
www.xilinx.com
Send Feedback
19