|
XC4VLX25-10SF363I Datasheet, PDF (3/9 Pages) Xilinx, Inc – Virtex-4 Family Overview | |||
|
◁ |
R
Virtex-4 Family Overview
SelectIO Technology
⢠Up to 960 user I/Os
⢠Wide selections of I/O standards from 1.5V to 3.3V
⢠Extremely high-performance
- 600 Mb/s HSTL & SSTL (on all single-ended I/O)
- 1 Gb/s LVDS (on all differential I/O pairs)
⢠True differential termination
⢠Selected low-capacitance I/Os for improved signal
integrity
⢠Same edge capture at input and output I/Os
⢠Memory interface support for DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
ChipSync Technology
⢠Integrated with SelectIO technology to simplify
source-synchronous interfaces
⢠Per-bit deskew capability built in all I/O blocks (variable
input delay line)
⢠Dedicated I/O and regional clocking resources (pin and
trees)
⢠Built in data serializer/deserializer logic in all I/O and
clock dividers
⢠Memory/Networking/Telecommunication interfaces up
to 1 Gb/s+ DDR
Digitally Controlled Impedance (DCI)
Active I/O Termination
⢠Optional series or parallel termination
⢠Temperature compensation
Configuration
⢠256-bit AES bitstream decryption provides intellectual
property (IP) security
⢠Improved bitstream error detection/correction capability
⢠Fast SelectMAP configuration
⢠JTAG support
⢠Readback capability
90 nm Copper CMOS Process
1.2V Core Voltage
Flip-Chip Packaging
⢠Pb-Free packages available with production devices.
System Blocks Specific to the Virtex-4 FX Family
RocketIO Multi-Gigabit Transceiver (MGT)
⢠Full-duplex serial transceiver (MGT) capable of
622 Mb/s to 6.5 Gb/s baud rates
⢠8B/10B, 64B/66B, user-defined FPGA logic, or no data
encoding/decoding
⢠Channel bonding support
⢠CRC generation and checking
⢠Programmable TX pre-emphasis or pre-equalization
⢠Programmable RX continuous time equalization
⢠Programmable RX decision feedback equalization
⢠On-chip RX AC coupling
⢠RX signal detect and loss of signal indicator
⢠TX driver electrical idle mode
⢠User dynamic reconfiguration using secondary
configuration bus
PowerPC 405 Processor RISC Core
⢠Embedded PowerPC 405 processor (PPC405) core
- Up to 450 MHz operation
- Five-stage data path pipeline
- 16 KB instruction cache
- 16 KB data cache
- Enhanced instruction and data on-chip memory
(OCM) controllers
- Additional frequency ratio options between
PPC405 and Processor Local Bus
⢠Auxiliary Processor Unit (APU) Interface for direct
connection from PPC405 to coprocessors in fabric
- APU can run at different clock rates
- Supports autonomous instructions: no pipeline stalls
- 32-bit instruction and 64-bit data
- 4-cycle cache line transfer
Tri-Mode Ethernet Media Access Controller
⢠IEEE 802.3 compliant
⢠Operates at 10, 100, and 1,000 Mb/s
⢠Supports tri-mode auto-detect
⢠Receive address filter
⢠Fully monolithic 1000Base-X solution with RocketIO
MGT
⢠Implements SGMII through RocketIO MGT to external
PHY device
⢠Supports multiple PHY (MII, GMII, etc.) interfaces
through an I/O resource
⢠Receive and transmit statistics available through
separate interfaces
⢠Separate host and client interfaces
⢠Support for jumbo frames
⢠Flexible, user-configurable host interface
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
3
|
▷ |