XC4VLX25-10SF363I Datasheet, PDF (2/9 Pages) Xilinx, Inc – Virtex-4 Family Overview

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Virtex-4 Family Overview
Table 1: Virtex-4 FPGA Family Members (Continued)
Configurable Logic Blocks (CLBs)⁽¹⁾
Block RAM
Device
Array⁽³⁾ Logic
Row x Col Cells
Max
Max
PowerPC
RocketIO Total Max
Distributed XtremeDSP 18 Kb Block
Processor Ethernet Transceiver I/O User
Slices RAM (Kb) Slices⁽²⁾ Blocks RAM (Kb) DCMs PMCDs Blocks
MACs
Blocks Banks I/O
XC4VSX25 64 x 40 23,040 10,240 160
128
128 2,304 4
0
N/A
N/A
N/A
9 320
XC4VSX35 96 x 40 34,560 15,360 240
192
192 3,456 8
4
N/A
N/A
N/A
11 448
XC4VSX55 128 x 48 55,296 24,576 384
512
320 5,760 8
4
N/A
N/A
N/A
13 640
XC4VFX12 64 x 24 12,312 5,472
86
32
36 648
4
0
1
2
N/A
9 320
XC4VFX20 64 x 36 19,224 8,544 134
32
68 1,224 4
0
1
2
8
9 320
XC4VFX40 96 x 52 41,904 18,624 291
48
144 2,592 8
4
2
4
12
11 448
XC4VFX60 128 x 52 56,880 25,280 395
128
232 4,176 12
8
2
4
16
13 576
XC4VFX100 160 x 68 94,896 42,176 659
160
376 6,768 12
8
2
4
20
15 768
XC4VFX140 192 x 84 142,128 63,168 987
192
552 9,936 20
8
2
4
24
17 896
Notes:
1. One CLB = Four Slices = Maximum of 64 bits.
2. Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
3. Some of the row/column array is used by the processors in the FX devices.
System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
• Up to twenty Digital Clock Manager (DCM) modules
- Precision clock deskew and phase shift
- Flexible frequency synthesis
- Dual operating modes to ease performance trade-off
decisions
- Improved maximum input/output frequency
- Improved phase shifting resolution
- Reduced output jitter
- Low-power operation
- Enhanced phase detectors
- Wide phase shift range
• Companion Phase-Matched Clock Divider (PMCD)
blocks
• Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
• 32 Global Clock networks
• Regional I/O and Local clocks
Flexible Logic Resources
• Up to 40% speed improvement over previous
generation devices
• Up to 200,000 logic cells including:
- Up to 178,176 internal registers with clock enable
(XC4VLX200)
- Up to 178,176 look-up tables (LUTs)
- Logic expanding multiplexers and I/O registers
• Cascadable variable shift registers or distributed
memory capability
500 MHz XtremeDSP Slices
• Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
• Optional pipeline stages for enhanced performance
• Optional 48-bit accumulator for multiply accumulate
(MACC) operation
• Integrated adder for complex-multiply or multiply-add
operation
• Cascadeable Multiply or MACC
• Up to 100% speed improvement over previous
generation devices.
500 MHz Integrated Block Memory
• Up to 10 Mb of integrated block memory
• Optional pipeline stages for higher performance
• Multi-rate FIFO support logic
- Full and Empty Flag support
- Fully programmable AF and AE Flags
- Synchronous/ Asynchronous Operation
• Dual-port architecture
• Independent read and write port width selection (RAM
only)
• 18 Kbit blocks (memory and parity/sideband memory
support)
• Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
• Byte-write capability (connection to PPC405, etc.)
• Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
• Up to 100% speed improvement over previous
generation devices.
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
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