DS601 Datasheet, PDF (3/4 Pages) Xilinx, Inc – LogiCORE IP Virtex-5 FPGA RocketIO GTX Transceiver

LogiCORE IP Virtex-5 FPGA RocketIO GTX Transceiver Wizard v1.7
Wrapper Overview
Figure 2 shows the block diagram of the wrapper, example design, and test bench produced by the
Wizard.
X-Ref Target - Figure 2
4 _{Test Bench}
3 _{Example Design}
5
FRAME_GEN
6
FRAME_CHECK
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Wrapper
GTX
Transceiver
Ports
Configuration
Parameters
2
GTX_DUAL
Transceiver
Tile(s)
Figure 2: Wrapper Block Diagram
DS601_02_051909
The wrapper comprises six components:
1. Wrapper: The specific GTX transceiver configuration parameters set with the Wizard.
2. GTX_DUAL Transceiver Tile(s): Instantiated tiles selected with the Wizard.
3. Example Design: Temporary top-level design that will be replaced with the actual application.
4. Test Bench: Top-level test bench to aid in simulation of the design.
5. FRAME_GEN Module: Generates a user-definable data stream for simulation analysis.
6. FRAME_CHECK Module: Tests for correct transmission of data stream for simulation analysis.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
The Virtex-5 FPGA RocketIO™ GTX Transceiver Wizard LogiCORE IP core is provided free of charge
under the terms of the Xilinx End User License Agreement. The core can be generated by the Xilinx ISE
CORE Generator software, which is a standard component of the Xilinx ISE Design Suite. This version
of the core can be generated using the ISE CORE Generator system v12.1 or higher. For more informa-
tion, please visit the Architecture Wizards web page. Information about additional Xilinx LogiCORE
DS601 April 19, 2010
www.xilinx.com
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Product Specification