DS601 Datasheet, PDF (1/4 Pages) Xilinx, Inc – LogiCORE IP Virtex-5 FPGA RocketIO GTX Transceiver

DS601 April 19, 2010
LogiCORE IP Virtex-5 FPGA
RocketIO GTX Transceiver
Wizard v1.7
Product Specification
Introduction
The LogiCORE™ IP Virtex^®-5 FPGA RocketIO™ GTX
Transceiver Wizard automates the task of creating HDL
wrappers ⁽¹⁾ to configure the high-speed serial GTX
transceivers in the Virtex-5 FXT and TXT sub-families.
The menu-driven interface allows one or more GTX
transceivers to be configured using pre-defined tem-
plates for popular industry standards, or from scratch,
to support a wide variety of custom protocols. The
Wizard produces a wrapper, an example design, and a
test bench for rapid integration and verification of the
serial interface with your custom function.
Features
• Creates customized HDL wrappers to configure
Virtex-5 family RocketIO GTX transceivers
• Users can configure Virtex-5 family GTX
transceivers to conform to industry standard
protocols using predefined templates, or tailor the
templates for custom protocols
• Templates include support for the following
specifications: Aurora (8B/10B and 64B/66B),
CPRI™, Fibre Channel 1x, Gigabit Ethernet, HD-
SDI, OBSAI, OC3, OC12, OC48, PCI EXPRESS^®
(PCIe^®) generation I and II, SATA 1.5 Gbps,
SATA 3 Gbps, Serial RapidIO, and XAUI
• Automatically configures analog settings
• Each custom wrapper includes example design,
test bench; and both implementation and
simulation scripts
• Supports 64B/66B and 64B/67B
encoding/decoding
LogiCORE IP Facts
Core Specifics
Supported Device
Family
Virtex-5 ⁽¹⁾ FXT/TXT
Provided with Core
Documentation
Design File Formats
Constraints File
Product Specification
Getting Started Guide
Verilog and VHDL
.ucf (user constraints file)
Verification
Example Design and Test Bench
Instantiation Template
Verilog or VHDL Wrapper
Design Tool Requirements
Xilinx Implementation
Tools
ISE^® 12.1⁽²⁾
Verification
Simulation
Synthesis
ISim 12.1
Mentor Graphics ModelSim 6.5c
and above
ISim 12.1
Mentor Graphics ModelSim 6.5c
and above
XST 12.1
Synopsys Synplify Pro D-2009.12
Support
Provided by Xilinx, Inc. at http://www.xilinx.com/support
1. For more information on the Virtex-5 devices,
see the Virtex-5 Family Overview [Ref 2]
2. ISE Service Packs can be downloaded
from http://www.xilinx.com/support/download.htm
1. See the LogiCORE IP Virtex-5 FPGA RocketIO GTX Transceiver Wizard Getting Started Guide [Ref 1] for an overview of the procedure to create a
wrapper.
© 2008-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. CPRI is a trademark of Siemens AG. PCI, PCI-SIG, PCI EXPRESS, PCIE, PCI-X, PCI HOT PLUG, MINI PCI, EXPRESSMODULE, and the PCI,
PCI-X, PCI HOT PLUG, and MINI PC design marks are trademarks, registered trademarks, and/or service marks of PCI-SIG. All other trademarks are the property
of their respective owners.
DS601 April 19, 2010
www.xilinx.com
1
Product Specification