DS481 Datasheet, PDF (3/5 Pages) National Semiconductor (TI) – Low Power RS-485/RS-422 Multipoint Transceiver with Sleep Mode

Utility Vector Logic (v1.00a)
Parameter-Port Dependencies
Table 3: Port and Parameter Dependencies
Name
Affects
Depends
Design Parameters
C_SIZE
Op1
0 to C_SIZE-1
C_SIZE
Op2
0 to C_SIZE-1
C_SIZE
Res
0 to C_SIZE-1
Port Signals
Op1
C_SIZE
Op2
C_SIZE
Res
C_SIZE
Relationship Description
Scale width of input bus
Scale width of input bus
Scale width of output bus
Scale width of input bus
Scale width of input bus
Scale width of output bus
Utility Vector Logic Register Descriptions
There are no registers in this core.
Utility Vector Logic Interrupt Descriptions
There are no interrupts associated with this core.
Utility Vector Logic Block Diagram
The Utility Vector Logic block diagram is shown in Figure 2.
X-Ref Target - Figure 2
All functions except “not”
Op1
Op2
f
Res
Function “not”
Op1
Res
DS481_02_100709
Figure 2: Utility Vector Logic Block Diagram
Design Implementation
Design Tools
The Utility Vector Logic design is handwritten.
Xilinx XST is the synthesis tool used for synthesizing the Utility Vector Logic device.
DS481 December 2, 2009
www.xilinx.com
3
Product Specification