DS481 Datasheet, PDF (1/5 Pages) National Semiconductor (TI) – Low Power RS-485/RS-422 Multipoint Transceiver with Sleep Mode

Utility Vector Logic (v1.00a)
DS481 December 2, 2009
Product Specification
Introduction
The Utility Vector Logic core takes two vector operands
and bit wise applies a logic function to generate a single
vector result. This core is intended as glue logic
between peripherals.
Features
• Configurable size of the vectors
• Configurable logical operation on vectors
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Spartan^®-3A/3A DSP, Spartan-3,
Spartan-3E, Automotive
Spartan 3/3E/3A/3A DSP, Spartan-6,
Virtex^®-4 /4Q/4QV, Virtex-5/5FX,
Virtex-6/6CX
Resources Used
Slices
LUTs
Min
Max
1
16 ⁽¹⁾
1
32 ⁽¹⁾
FFs
0
0
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats VHDL
Design Tool Requirements
Xilinx Implementation
Tools
ISE^® 11.4 or later
Verification
ModelSim PE/SE 6.4b or later
Simulation
ModelSim PE/SE 6.4b or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
1. For C_SIZE=32. The count increases with C_SIZE.
© 2003-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS481 December 2, 2009
www.xilinx.com
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Product Specification