XCR5064 Datasheet, PDF (2/16 Pages) Xilinx, Inc – On-chip supervoltage generation

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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
XPLA Architecture
Figure 1 shows a high level block diagram of a 64 macrocell
device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. The 6 control terms can individually be con-
figured as either SUM or PRODUCT terms, and are used to
control the preset/reset and output enables of the 16 mac-
rocells’ flip-flops. In addition, two of the control terms can
be used as clock signals (see Macrocell Architecture Sec-
tion for details). The PAL array consists of a programmable
AND array with a fixed OR array, while the PLA array con-
sists of a programmable AND array with a programmable
OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t_PD of the XCR5064C device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 2.0 ns.
So the total pin-to-pin t_PD for the XCR5064C using six to 37
product terms is 9.5 ns (7.5 ns for the PAL + 2.0 ns for the
PLA)..
MC0
MC1
LOGIC
36
I/O
BLOCK
MC15
16
16
MC0
MC1
LOGIC
36
I/O
BLOCK
MC15
16
16
Figure 1: Xilinx XPLA CPLD Architecture
MC0
36
LOGIC
MC1
BLOCK
I/O
MC15
16
16
ZIA
MC0
36
LOGIC
MC1
BLOCK
I/O
MC15
16
16
SP00439
DS044 (v1.1) February 10, 2000
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