XCR5064 Datasheet, PDF (13/16 Pages) Xilinx, Inc – On-chip supervoltage generation

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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
AC Electrical Characteristics¹ For Industrial Grade Devices
Industrial: -40°C ≤ T_AMB ≤ +85°C; 4.5V ≤ V_CC ≤ 5.5V
Symbol
Parameter
I10
Min. Max.
t_{PD_PAL} Propagation delay time, input (or feedback node) to output through PAL 2
10
t_{PD_PLA} Propagation delay time, input (or feedback node) to output through
3
12
PAL + PLA
t_CO
Clock to out (global synchronous clock from pin)
2
7
t_{SU_PAL} Setup time (from input or feedback node) through PAL
6
t_{SU_PLA} Setup time (from input or feedback node) through PAL + PLA
8
t_H
Hold time
0
t_CH
Clock High time
4
t_CL
Clock Low time
4
t_R
Input Rise time
20
t_F
f_MAX1
f_MAX2
f_MAX3
Input Fall time
Maximum FF toggle rate² (1/t_CH + t_CL)
Maximum internal frequency² (1/t_SUPAL + t_CF)
Maximum external frequency² (1/t_SUPAL + t_CO)
20
125
95
77
t_BUF
Output buffer delay time
2.5
t_{PDF_PAL} Input (or feedback node) to internal feedback node delay time through
7.5
PAL
t_{PDF_PLA} Input (or feedback node) to internal feedback node delay time through
9.5
PAL+PLA
t_CF
Clock to internal feedback node delay time
4.5
t_INIT
Delay from valid V_CC to valid reset
50
t_ER
Input to output disable^{2, 3}
10
t_EA
Input to output valid²
10
t_RP
Input to register preset²
11
t_RR
Input to register reset²
11
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output C_L = 5 pF.
I12
Min. Max.
2
12
3
14
2
8
7
9
0
5
5
20
20
100
80
67
2.5
9.5
11.5
5.5
50
12
12
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
µs
ns
ns
ns
ns
13
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DS044 (v1.1) February 10, 2000
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