XC1701 Datasheet, PDF(2/10 Page) Xilinx, Inc – On-chip address counter, incremented by each rising

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XC1701 Datasheet, PDF (2/10 Pages) Xilinx, Inc – On-chip address counter, incremented by each rising

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XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conï¬guration PROMs

Pin Description

DATA

Data output, 3-stated when either CE or OE are inactive.

During programming, the DATA pin is I/O. Note that OE can

be programmed to be either active High or active Low.

CLK

Each rising edge on the CLK input increments the internal

address counter, if both CE and OE are active.

RESET/OE

When High, this input holds the address counter reset and

3-states the DATA output. The polarity of this input pin is

programmable as either RESET/OE or OE/RESET. To

avoid confusion, this document describes the pin as

RESET/OE, although the opposite polarity is possible on all

devices. When RESET is active, the address counter is

held at zero, and the DATA output is 3-stated. The polarity

of this input is programmable. The default is active High

RESET, but the preferred option is active Low RESET,

because it can be driven by the FPGAâs INIT pin.

The polarity of this pin is controlled in the programmer inter-

face. This input pin is easily inverted using the Xilinx HW-

130 Programmer. Third-party programmers have different

methods to invert this pin.

When High, this pin disables the internal address counter,

3-states the DATA output, and forces the device into low-ICC

standby mode.

CEO

Chip Enable output, to be connected to the CE input of the

next SCP in the daisy chain. This output is Low when the

CE and OE inputs are both active AND the internal address

counter has been incremented beyond its Terminal Count

(TC) value. In other words: when the PROM has been read,

CEO will follow CE as long as OE is active. When OE goes

inactive, CEO stays High until the PROM is reset. Note that

OE can be programmed to be either active High or active

Low.

VPP

Programming voltage. No overshoot above the speciï¬ed

max voltage is permitted on this pin. For normal read oper-

ation, this pin must be connected to VCC. Failure to do so

may lead to unpredictable, temperature-dependent opera-

tion and severe problems in circuit debugging. Do not leave

VPP ï¬oating!

VCC and GND

Positive supply and ground pins.

Serial PROM Pinouts

Pin Name

DATA

CLK

RESET/OE (OE/RESET)

GND

CEO

VPP

VCC

Capacity

Device

XC1701L

XC1701

XC17512L

8-Pin

PDIP

20-Pin

SOIC

20-Pin

PLCC

Conï¬guration Bits

1,048,576

524,288

Number of Conï¬guration Bits, Including

Header for all Xilinx FPGAs and Compatible

SCP Type

Device

XC4010XL

XC4013XL

XC4020E

XC4020XL

XC4025E

XC4028XL

XC4028EX

XC4036EX

XC4036XL

XC4044XL

XC4052XL

XC4062XL

XC4085XL

Conï¬guration Bits

283,424

393,623

329,312

521,880

422,176

668,184

832,528

1,014,928

1,215,368

1,433,864

1,924,992

SPROM

XC17512L

XC1701

XC17512L

XC1701

XC1701L

XC1701

XC1701L

XC1701L +

XC17256L

XC1701L +

XC17512L

2 x XC1701L

5-2

December 10, 1997 (Version 1.1)

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