DS635 Datasheet, PDF (2/37 Pages) Xilinx, Inc – Enhanced Double Data Rate (DDR) support

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Key Feature Differences from Commercial XC Devices
• AEC-Q100 device qualification and full production part
approval process (PPAP) documentation support
available in both extended temperature I- and
Q-Grades
• Guaranteed to meet full electrical specification over the
T_J = –40°C to +125°C temperature range (Q-Grade)
• XA Spartan-3E devices are available in the -4 speed
grade only.
• PCI-66 is not supported in the XA Spartan-3E FPGA
product line.
• The readback feature is not supported in the XA
Spartan-3E FPGA product line.
• XA Spartan-3E devices are available in Step 1 only.
• JTAG configuration frequency reduced from 30 MHz to
25 MHz.
• Platform Flash is not supported within the XA family.
• XA Spartan-3E devices are available in Pb-free
packaging only.
• MultiBoot is not supported in XA versions of this
product.
• The XA Spartan-3E device must be power cycled prior
to reconfiguration.
Table 1: Summary of XA Spartan-3E FPGA Attributes
Device
System
Gates
Equivalent
Logic
Cells
CLB Array
(One CLB = Four Slices)
Total Total
Rows Columns CLBs Slices
XA3S100E 100K
2,160
22
16
240
960
XA3S250E ^250K
5,508
34
26
612 2,448
XA3S500E ^500K
10,476
46
34
1,164 4,656
XA3S1200E ^{1200K 19,512}
60
46
2,168 8,672
XA3S1600E 1600K 33,192
76
58
3,688 14,752
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
Distributed
RAM bits⁽¹⁾
15K
38K
73K
136K
231K
Block
RAM
bits⁽¹⁾
72K
216K
360K
504K
648K
Maximum
Dedicated
Maximum Differential
Multipliers DCMs User I/O I/O Pairs
4
2
108
40
12
4
172
68
20
4
190
77
28
8
304
124
36
8
376
156
Architectural Overview
The XA Spartan-3E family architecture consists of five fun-
damental programmable functional elements:
• Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
• Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
• Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
• Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
• Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in Figure 1. A ring
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XA3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XA3S100E has only one DCM at the top and bottom, while
the XA3S1200E and XA3S1600E add two DCMs in the mid-
dle of the left and right sides.
The XA Spartan-3E family features a rich network of traces
that interconnect all five functional elements, transmitting
signals among them. Each functional element has an asso-
ciated switch matrix that permits multiple connections to the
routing.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
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