DS600 Datasheet, PDF (10/11 Pages) Maxim Integrated Products – 0.5 Accurate Analog-Output Temperature Sensor

XA95144XL Automotive CPLD
R
a. The current flow can go into V_CCIO and affect a user
voltage regulator.
b. It can also increase undesired leakage current
associated with the device.
c. If done for too long, it can reduce the life of the
device.
8. Do not rely on the I/O states before the CPLD
configures.
9. Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
10. Ensure external JTAG terminations for TMS, TCK, TDI,
TDO comply with IEEE 1149.1. All Xilinx CPLDs have
internal weak pull-ups of ~50 kΩ on TDI, TMS, and
TCK.
11. Attach all CPLD V_CC and GND pins in order to have
necessary power and ground supplies around the
CPLD.
12. Decouple all V_CC and V_CCIO pins with capacitors of
0.01 μF and 0.1 μF closest to the pins for each
V_CC/V_CCIO-GND pair.
Recommendations
The following recommendations are for all automotive appli-
cations.
1. Use strict synchronous design (only one clocking event)
if possible. A synchronous system is more robust than
an asynchronous one.
2. Include JTAG stakes on the PCB. JTAG stakes can be
used to test the part on the PCB. They add benefit in
reprogramming part on the PCB, inspecting chip
internals with INTEST, identifying stuck pins, and
inspecting programming patterns (if not secured).
3. XA9500XL Automotive CPLDs work with any power
sequence, but it is preferable to power the V_CCI
(internal V_CC) before the V_CCIO for the applications in
which any glitches from device I/Os are unwanted.
4. Do not disregard report file warnings. Software
identifies potential problems when compiling, so the
report file is worth inspecting to see exactly how your
design is mapped onto the logic.
5. Understand the Timing Report. This report file provides
a speed summary along with warnings. Read the timing
file (*.tim) carefully. Analyze key signal chains to
determine limits to given clock(s) based on logic
analysis.
6. Review Fitter Report equations. Equations can be
shown in ABEL-like format, or can also be displayed in
Verilog or VHDL formats. The Fitter Report also
includes switch settings that are very informative of
other device behaviors.
7. Let design software define pinouts if possible. Xilinx
CPLD software works best when it selects the I/O pins
and manages resources for users. It can spread signals
around and improve pin-locking. If users must define
pins, plan resources in advance.
8. Perform a post-fit simulation for all speeds to identify
any possible problems (such as race conditions) that
might occur when fast-speed silicon is used instead of
slow-speed silicon.
9. Distribute SSOs (Simultaneously Switching Outputs)
evenly around the CPLD to reduce switching noise.
10. Terminate high speed outputs to eliminate noise caused
by very fast rising/falling edges.
10
www.xilinx.com
DS600 (v1.1) April 3, 2007
Product Specification