EN016 Datasheet, PDF (1/3 Pages) Xilinx, Inc – The FIFO16 does not correctly generate the ALMOST EMPTY

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Virtex-4 XC4VLX160CES and
XC4VLX200CES Errata
EN016 (v1.2) February 15, 2006
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Introduction
Thank you for your interest in the Xilinx Virtex™-4 family of FPGAs. We are pleased to provide to you engineering samples
of the Virtex-4 XC4VLX160CES and XC4VLX200CES devices. Although Xilinx has made every effort to ensure the highest
possible quality, these devices are subject to the limitations described in this errata notice.
Devices
These errata apply to the XC4VLX160CES and XC4VLX200CES devices as shown in Table 1.
Table 1: XC4VLX160 and XC4VLX200 Devices Affected by These Errata
Devices
XC4VLX160CES
JTAG ID (Revision Code): 0, 3
XC4VLX200CES
JTAG ID (Revision Code): 0, 3
Packages
All
Speed Grades All
Hardware Errata Details
This section provides a detailed description of each hardware issue known at the release time of this document.
FIFO16
The FIFO16 does not correctly generate the ALMOST EMPTY, EMPTY, ALMOST FULL, and FULL flags after the following
sequence occurs:
1. Read or Write has reached the threshold value of ALMOST EMPTY OFFSET or ALMOST FULL OFFSET.
2. A single Read or Write operation is performed, followed by a simultaneous Read or Write operation, when active Read
and Write clock edges are very close together.
Unexpected or corrupt data can occur as a result of the flag failures, even if the ALMOST EMPTY or ALMOST FULL flags
are not being used.
This issue does not happen in FIFO16 applications where Read and Write never occur simultaneously. Workarounds (down-
loadable macros) are available for users who are performing simultaneous Read/Writes. Not all workarounds will achieve
data sheet performance. See Xilinx answer record 22462 for more details, workaround solutions, and corresponding perfor-
mance information.
Operational Guidelines
Design Software Requirements
The devices covered by these errata, unless otherwise specified, require the following Xilinx development software installa-
tions.
• Speed specification v1.57 (or later) and Xilinx software ISE 7.1i Service Pack 4 (SP4) or later is required when
designing for the devices covered by this errata. Contact Xilinx technical support for SP4 help. Updates are available
on the following web page:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The stepping should be set to "1" in the constraint file (UCF file):
CONFIG STEPPING = “1”;
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All other trademarks are the property of their respective owners.
EN016 (v1.2) February 15, 2006
www.xilinx.com
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Errata Notification