DS107 Datasheet, PDF (1/4 Pages) Xilinx, Inc – Internal 3-state bus capability

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DS107-1 (v2.0) August 9, 2013
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Spartan-XL 3.3V FPGA
Automotive IQ Family:
Introduction and Ordering
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Introduction
The Spartan™-XL 3.3V FPGA Automotive IQ product family
is a high-volume production FPGA solution that delivers all
the key requirements for ASIC replacement up to 40,000
gates. These requirements include high-performance,
on-chip RAM, core solutions, and prices that, in high vol-
ume, approach and in many cases, are equivalent to mask
programmed ASIC devices. By streamlining the Spartan-XL
series feature set, leveraging process technology and
focusing on total cost management, the Spartan-XL series
delivers the key features required by ASIC and other
high-volume logic users while avoiding the initial cost, long
development cycles, and inherent risk of conventional
ASICs.
Features
• Guaranteed to meet full electrical specifications over
T_J = –40°C to +125°C
• ASIC replacement FPGA for high-volume production
with on-chip RAM
• Density up to 1,862 logic cells or 40,000 system gates
• Streamlined feature set based on XC4000 architecture
• Broad set of AllianceCORE™ and LogiCORE™
predefined solutions available
• Unlimited reprogrammability
• System level features
- On-chip SelectRAM™ memory
- Full readback capability for program verification
and internal node observability
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal networks
- IEEE 1149.1-compatible Boundary Scan logic
- Footprint compatibility in common packages
• Fully supported by powerful Xilinx development system
- ISE Foundation™ Series: Integrated, shrink-wrap
software
- ISE Alliance Series™: Dozens of PC and
workstation third party development systems
supported
- Fully automatic mapping, placement and routing
• 3.3V supply for low power with 5V tolerant I/Os
• Power down input
• Higher performance
• Faster carry logic
• More flexible high-speed clock network
• Latch capability in Configurable Logic Blocks
• Input fast capture latch
• Optional mux or 2-input function generator on outputs
• 12 mA or 24 mA output drive
• Enhanced Boundary Scan
• Express Mode configuration
• Refer to Spartan-XL and Spartan FPGAs complete
data sheet (DS060) for product description, AC and DC
specifications
Table 1: Spartan-XL Field Programmable Gate Arrays
Device
Logic
Cells
Typical
Max System
Gate Range
Gates
(Logic and RAM)⁽¹⁾
CLB
Matrix
XCS05XL
238
5,000
2,000-5,000
10 x 10
XCS10XL
466
10,000
3,000-10,000
14 x 14
XCS20XL
950
20,000
7,000-20,000
20 x 20
XCS30XL
1,368
30,000
10,000-30,000 24 x 24
XCS40XL
1,862
40,000
13,000-40,000 28 x 28
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Total
CLBs
100
196
400
576
784
Max.
Total
No. of Avail. Distributed
Flip-flops User I/O RAM Bits
360
77
3,200
616
112
6,272
1,120
160
12,800
1,536
192
18,432
2,016
224
25,088
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DS107-1 (v2.0) August 9, 2013
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Product Specification