X1243 Datasheet, PDF (9/18 Pages) Xicor Inc. – Real Time Clock/Calendar/Alarm with EEPROM

X1243
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
Slave
Address
Word
Address 1
Word
Address 0
S
t
Data
o
p
1
111 0 00000
A
A
A
A
C
C
C
C
K
K
K
K
Figure 6. Byte Write Sequence
7 bytes
23 bytes
address
=6
address pointer
ends here
Addr = 7
address
40
address
63
Figure 7. Writing 30 bytes to a 64-byte page starting at adress 40.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
Slave
r
t
Address
Word
Address 1
Word
Address 0
(1 < n < 64)
S
Data
Data
t
(1)
(n)
o
p
1
1 1 10 0 00 00
A
A
C
C
K
K
A
C
K
A
C
K
Figure 8. Page Write Sequence
Page Write
The X1243 has a page write operation. It is initiated in
the same manner as the byte write operation; but instead
of terminating the write cycle after the first data byte is
transferred, the master can transmit up to 63 more bytes
to the memory array and up to 7 more bytes to the
clock/control registers. (Note: Prior to writing to the
CCR, the master must write a 02h, then 06h to the sta-
tus register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control Reg-
isters” on page 6.)
After the receipt of each byte, the X1243 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. If the master begins writing at location 40 of the
memory and loads 30 bytes, then the first 23 bytes are
written to addresses 40 through 63, and the last 7
bytes are written to columns 0 through 6. Afterwards,
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