X1243 Datasheet, PDF (11/18 Pages) Xicor Inc. – Real Time Clock/Calendar/Alarm with EEPROM

X1243
Signals from
the Master
S
t
a
Slave
S
t
r Address
o
t
p
SDA Bus
Signals from
the Slave
1
11 11
A
C
K
Data
Figure 10. Current Address Read Sequence
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 11 for the address,
acknowledge, and data transfer sequence.
In a similar operation, called “Set Current Address,”
the device sets the address if a stop is issued instead of
the second start shown in Figure 11. The X1243 then
goes into standby mode after the stop and all bus activity
will be ignored until a start is detected. This operation
loads the new address into the address counter. The next
Current Address Read operation will read from the
newly loaded address. This operation could be useful
if the master knows the next address it needs to read,
but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory
contents to be serially read during one operation. At
the end of the address space the counter “rolls over” to
the start of the address space and the device continues
to output data for each acknowledge received. Refer
to Figure 12 for the acknowledge and data transfer
sequence.
S
S
Signals from
the Master
t
a
r
Slave
Address
Word
Address 1
Word
Address 0
t
a ^Slave
r Address
S
t
o
t
t
p
SDA Bus
Signals from
the Slave
1
1 1 1 0 0 0 0 00
A
A
C
C
K
K
1
A
C
K
1111
A
C
K
Data
Figure 11. Random Address Read Sequence
11