X24F128 Datasheet, PDF (8/16 Pages) Xicor Inc. – 2-Wire SerialFlash with Block Lock TM Protection

X24F128
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” program opera-
tion. The master issues the start condition and the
Slave Address Byte with the R/W bit low, receives an
acknowledge, then issues Address Byte 1, receives
another acknowledge, then issues Address Byte 0
containing the address of the byte to be read. After the
device acknowledges receipt of Address Byte 0, the
master issues another start condition and the Slave
Address Byte with the R/W bit set to one. This is
followed by an acknowledge and then eight bits of data
from the device. The master terminates the read oper-
ation by not responding with an acknowledge and then
issuing a stop condition. Refer to figure 8 for the
address, acknowledge, and data transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the
second start shown in figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
Figure 8. Random Read Sequence
ation is that the new address is loaded into the
address counter, but no data is output by the device.
The next Current Address Read operation will read
from the newly loaded address.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first byte is trans-
mitted as with the other modes; however, the master
now responds with an acknowledge, indicating it
requires additional data. The device continues to
output data for each acknowledge received. The
master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all byte
addresses, allowing the entire memory contents to be
read during one operation. At the end of the address
space the counter “rolls over” to address 0000h and the
device continues to output data for each acknowledge
received. Refer to figure 9 for the acknowledge and data
transfer sequence.
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
S
T
A
R
SLAVE
ADDRESS
T
S1 0 1 0
0
ADDRESS
BYTE 1
ADDRESS
BYTE 0
S
T
SLAVE
A
R
ADDRESS
T
S
1
A
A
A
A
C
C
C
C
K
K
K
K
S
T
O
P
P
DATA
7012 ILL F11.1
Figure 9. Sequential Read Sequence
SIGNALS
FROM THE
MASTER
SDA BUS
SLAVE
ADDRESS
S
1
A
A
A
S
C
C
C
T
K
K
K
O
P
P
SIGNALS
FROM THE
SLAVE
A
C
K
DATA
(1)
DATA
(2)
DATA
(n–1)
DATA
(n)
7012 ILL F12.1
8