X5163 Datasheet, PDF (7/21 Pages) Xicor Inc. – CPU Supervisor with 16Kbit SPI EEPROM

X5163/X5165 – Preliminary Information
Figure 5. Read EEPROM Array Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
Instruction
SI
16 Bit Address
15 14 13
3210
High Impedance
SO
Data Out
7 654321 0
MSB
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
In the locked state (Programmable ROM Mode) the
WP pin is LOW and the nonvolatile bit WPEN is “1”.
This mode disables nonvolatile writes to the device’s
Status Register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to “0” blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to “1”
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.
REV 1.1 3/5/01
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Characteristics subject to change without notice. 7 of 21