X9251 Datasheet, PDF (6/25 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) Potentiometer

X9251
PRINCIPLES OF OPERATION
The X9251 is an integrated circuit incorporating four
DCPs and their associated registers and counters, and
a serial interface providing direct communication
between a host and the potentiometers.
DCP Description
Each DCP is implemented with a combination of
resistor elements and CMOS switches. The physical
ends of each DCP are equivalent to the fixed terminals
of a mechanical potentiometer (R_H and R_L pins). The
RW pin is an intermediate node, equivalent to the
wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V_CC and the voltages applied to the
potentiometer pins provided that V_CC is always more
positive than or equal to V_H, V_L, and V_W, i.e., V_CC ≥ V_H,
V_L, V_W. The V_CC ramp rate specification is always in
effect.
Figure 1. Detailed Potentiometer Block Diagram
One of Four Potentiometers
#: 0, 1, 2, or 3
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
8
DR#2
R_H
SERIAL
BUS
INPUT
DR#1
8
PARALLEL
BUS
DR#3
INPUT
WIPER
COUNTER DCP
---
CORE
R_W
DECODE
COUNTER
REGISTER
(WCR#)
IF WCR = 00[H] then R_W is closet to R_L
IF WCR = FF[H] then R_W is closet to R_H
UP/DN
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
CLK
R_L
REV 1.3.3 2/10/04
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Characteristics subject to change without notice. 6 of 25