X9251 Datasheet, PDF (4/25 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) Potentiometer

X9251
PIN CONFIGURATION
SO
A0
R_W3
R_H3
R_L3
NC
V_CC
R_L0
R_H0
R_W0
CS
WP
SOIC/TSSOP
1
24
2
23
3
22
4
21
5
20
6
19
X9251
7
18
8
17
9
16
10
15
11
14
12
13
HOLD
SCK
R_L2
R_H2
R_W2
NC
V_SS
R_W1
R_H1
R_L1
A1
SI
CSP
1
2
3
4
A
R_W0
R_L0
B
V_CC
C
NC
D
R_L3
E
R_W3
F
CS
A₁
R_L1
WP
SI
R_W1
R_H0
R_H1
V_SS
R_H3
R_H2
NC
SO
HOLD R_W2
A₀
SCK
R_L2
Top View–Bumps Down
PIN ASSIGNMENTS
Pin
(SOIC)
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
6, 19
Pin
(CSP)
E2
F2
F1
D2
E1
C1
B1
C2
A1
A2
B2
B3
A3
A4
C3
B4
C4
E4
D3
F4
F3
E3
D1, D4
Symbol
SO
A0
R_W3
R_H3
R_L3
V_CC
R_L0
R_H0
R_W0
CS
WP
SI
A1
R_L1
R_H1
R_W1
V_SS
R_W2
R_H2
R_L2
SCK
HOLD
NC
Function
Serial Data Output for SPI bus
Device Address for SPI bus. (See Note 1)
Wiper Terminal of DCP3
High Terminal of DCP3
Low Terminal of DCP3
System Supply Voltage
Low Terminal of DCP0
High Terminal of DCP0
Wiper Terminal of DCP0
SPI bus. Chip Select active low input
Hardware Write Protect – active low
Serial Data Input for SPI bus
Device Address for SPI bus. (See Note 1)
Low Terminal of DCP1
High Terminal of DCP1
Wiper Terminal of DCP1
System Ground
Wiper Terminal of DCP2
High Terminal of DCP2
Low Terminal of DCP2
Serial Clock for SPI bus
Device select. Pauses the SPI serial bus.
No Connect
Note 1: A0–A1 device address pins must be tied to a logic level.
REV 1.3.3 2/10/04
www.xicor.com
Characteristics subject to change without notice. 4 of 25