X40420 Datasheet, PDF (6/25 Pages) Xicor Inc. – Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

X40420/X40421 – Preliminary
Resetting the V_TRIPx Voltage
To reset a V_TRIPx voltage, apply the programming voltage
(Vp) to the WDO pin before a START condition is set up
on SDA. Next, issue on the SDA pin the Slave Address
A0h followed by the Byte Address 03h for V_TRIP1 and
0Bh for V_TRIP2, followed by 00h for the Data Byte in order
to reset V_TRIPx. The STOP bit following a valid write oper-
ation initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation.
After being reset, the value of V_TRIPx becomes a nominal
value of 1.7V or lesser.
Note: This operation does not corrupt the memory array.
System Battery Switch
As long as V_CC exceeds the low voltage detect threshold
V_TRIP, V_OUT is connected to V_CC through a 5 Ohm (typi-
cal) switch. When the V_CC has fallen below V1_TRIP, then
V_CC is applied to V_OUT if V_CC is or equal to or greater
than V_BATT – 0.03V. When V_CC drops to less than V_BATT
– 0.03V, then V_OUT is connected to V_BATT through an 80
Ohm (typical) switch. V_OUT typically supplies the system
static RAM voltage, so the switchover circuit operates to
protect the contents of the static RAM during a power fail-
ure. Typically, when V_CC has failed, the SRAMs go into a
lower power state and draw much less current than in
their active mode. When V_CC returns, V_OUT switches
back to V_CC when V_CC exceeds V_BATT + 0.03V. There is
a 60mV hysteresis around this battery switch threshold to
prevent oscillations between supplies.
While V_CC is connected to V_OUT the BATT-ON pin is
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
during normal operation.
Condition
V_CC > V_TRIP1
V_CC > V_TRIP1 &
V_BATT = 0
0 ≤ V_CC ≤ V_TRIP1
and V_CC < V_BATT
Mode of Operation
Normal Operation
Normal Operation without battery
backup capability
Battery Backup mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh. It
can only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation. Prior to
writing to the Control Register, the WEL and RWEL bits
must be set using a two step process, with the whole
sequence requiring 3 steps. See "Writing to the Control
Registers" on page 8.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0, and BP. The X40420 will not
acknowledge any data bytes written after the first byte is
entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
Operation
The device is in normal operation with V_CC as long as
V_CC > V_TRIP1. It switches to the battery backup mode
when V_CC goes away.
765 4
PUP1 WD1 WD0 BP
3 210
0 RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 5. Sample V_TRIP Reset Circuit
V_P
V_TRIP1
Adj.
V2FAIL
RESET
V_TRIP2
Adj.
4.7K
1
14
6
13
X40420
2
9
7
8
Adjust
Run
µC
SCL
SDA
REV 1.2.14 7/12/02
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Characteristics subject to change without notice. 6 of 25