X40420 Datasheet, PDF (3/25 Pages) Xicor Inc. – Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

X40420/X40421 – Preliminary
PIN DESCRIPTION (Continued)
Pin Name
Function
4
WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
5
MR
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t_PURST thereafter. It has an internal pull up resistor.
6 RESET/ RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever
RESET
V_CC falls below V_TRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t_PURST) on power up. It will also stay active until manual reset is released
and for t_PURST thereafter.
RESET Output. (X40420) This pin is an active HIGH open drain output which goes HIGH when-
ever V_CC falls below V_TRIP1 voltage or if manual reset is asserted. This output stays active for the
programmed time period (t_PURST) on power up. It will also stay active until manual reset is released
and for t_PURST thereafter.
7
V_SS
Ground
8
SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9
SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
WP
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers).
It has an internal pull down resistor. (>10MΩ typical)
11
V_BATT Battery Supply Voltage. This input provides a backup supply in the event of a failure of the
primary V_CC voltage. The V_BATT voltage typically provides the supply voltage necessary to
maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is
not used, connect V_BATT to ground.
12
V_OUT Output Voltage. (V)
V_OUT = V_CC if V_CC > V_TRIP1.
IF V_CC < V_TRIP1
then V_OUT = V_CC if V_CC > V_BATT + 0.03V
else V_OUT = V_BATT (ie if V_CC < V_BATT – 0.03V)
Note: There is hysteresis around V_BATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to V_OUT to ensure stability.
13 BATT-ON Battery On. This CMOS output goes HIGH when the V_OUT switches to V_BATT and goes LOW
when V_OUT switches to V_CC. It is used to drive an external PNP pass transistor when V_CC = V_OUT
and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the V_CC supply is fully functional. In the event of a V_CC failure, the battery voltage is applied to the
V_OUT pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data–there is no
communication at this time.
14
V_CC
Supply Voltage
REV 1.2.14 7/12/02
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Characteristics subject to change without notice. 3 of 25