X25C02 Datasheet, PDF (5/14 Pages) Xicor Inc. – SPI Serial E2PROM

X25C02
Operational Notes
The X25C02 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Figure 1. Read Operation Sequence
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come HIGH at the proper clock count in
order to start a write cycle.
The “write enable” latch is reset when WP is brought LOW.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
INSTRUCTION
SI
BYTE ADDRESS
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
5432
10
3843 FHD F04.1
Figure 2. Set Write Enable Latch Sequence
CS
SCK
01234567
SI
HIGH IMPEDANCE
SO
3843 FHD F05.1
5