X25C02 Datasheet, PDF (1/14 Pages) Xicor Inc. – SPI Serial E2PROM

APPLICATION NOTES
AVA I L A B L E
X25C02 ^{AN9 • AN18 • AN31 • AN37 • AN40}
2K
X25C02
SPI Serial E²PROM
256 x 8 Bit
FEATURES
• 1MHz Clock Rate
• 256 X 8 Bits
—4 Byte Page Mode
• Low Power CMOS
—150µA Standby Current
—2mA Active Current
• 5V Power Supply
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
• Available Packages
—8-Lead MSOP
—8-Lead PDlP
—8-Lead SOIC
FUNCTIONAL DIAGRAM
DESCRIPTION
The X25C02 is a CMOS 2048-bit serial E²PROM, inter-
nally organized as 256 x 8. The X25C02 features a serial
interface and software protocol allowing operation on a
simple three-wire bus. The bus signals are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select
(CS) input, allowing any number of devices to share the
same bus.
The X25C02 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25C02 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25C02 disabling all write attempts, thus provid-
ing a mechanism for limiting end user capability of
altering the memory.
The X25C02 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct Write^™ is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3843-1.6 6/10/96 T5/C1/D1 NS
X ⁶⁴
DECODE
LOGIC
256 BYTE ARRAY
(64 X 32)
4
8
Y DECODE
DATA REGISTER
3843 FHD F01
Characteristics subject to change without notice
1