X24128 Datasheet, PDF (5/17 Pages) Xicor Inc. – 400KHz 2-Wire Serial E2PROM with Block Lock

X24128
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S₀, S₁, and S₂. This allows up to 8
devices to share a single bus. These bits are
compared to the S₀, S₁, and S₂ device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a read operation is selected. When it is zero then
a write operation is selected. Refer to figure 4. After
loading the Slave Address Byte from the SDA bus, the
device compares the device type bits with the value
“1010” and the device select bits with the status of the
device select input pins. If the compare is not successful,
no acknowledge is output during the ninth clock cycle
and the device returns to the standby mode.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in figure 4.
The internal organization of the E² array is 512 pages by
32 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 5 of the Word Address Byte 0. The byte
address is contained in bits 4 through 0 of the Word
Address Byte 0. See figure 4.
Figure 4. Device Addressing
DEVICE TYPE
IDENTIFIER
DEVICE
SELECT
1 0 1 0 S ₂ S1 S0 R/ W
SLAVE ADDRESS BYTE
HIGH ORDER WORD ADDRESS
0 0 A13 A12 A11 A10 A9 A8
X24128 WORD ADDRESS BYTE 1
LOW ORDER WORD ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
WORD ADDRESS BYTE 0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
7027 FM 06
5