X24128 Datasheet, PDF (13/17 Pages) Xicor Inc. – 400KHz 2-Wire Serial E2PROM with Block Lock

X24128
Bus Timing
SCL
SDA IN
tSU:STA
tF
tHIGH
tLOW
tHD:STA tHD:DAT
t _SU:DAT
tR
t _SU:STO
tAA
t _DH
t _BUF
SDA OUT
Write Cycle Limits
7027 FM 14
Symbol
Parameter
Min.
Typ.⁽⁵⁾
Max.
Units
T_WC(6)
Write Cycle Time
5
10
ms
7027 FRM T11
Notes: (5) Typical values are for T_A = 25°C and nominal supply voltage (5V).
(6) t_WR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24128 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
Bus Timing
SCL
SDA
8th BIT
WORD n
ACK
ST OP
CONDITION
t _WR
START
CONDITION
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
100
RMIN
=
VCC _MAX
IOL _MIN
=1.8KΩ
80
RMAX
=
tR
CBUS
60
MAX.
RESISTANCE
40
20 _MIN.
RESISTANCE
0
0 20 40 60
80 100 120
BUS CAPACITANCE (pF)
7027 FM 16
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
7027 FM 15
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance _{7027 FM 17}
13