X25644 Datasheet, PDF(4/15 Page) Xicor Inc. – Programmable Watchdog Timer w/Serial E 2 PROM

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X25644 Datasheet, PDF (4/15 Pages) Xicor Inc. – Programmable Watchdog Timer w/Serial E 2 PROM

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X25644/46

X25324/26

X25164/66

The Watchdog Timer bits, WD0 and WD1, select the

Watchdog Time-out Period. These nonvolatile bits are

programmed with the WRSR instruction.

Status Register Bits

WD1

WD0

Watchdog Time-out

(Typical)

1.4 Seconds

600 Milliseconds

200 Milliseconds

Disabled

7029 FRM T05

The FLAG bit shows the status of a volatile latch that can

be set and reset by the system using the SFLB and RFLB

instructions. The Flag bit is automatically reset upon

power up.

The nonvolatile WPEN bit is programmed using the

WRSR instruction. This bit works in conjunction with the

WP pin to provide Programmable Hardware Write Protec-

tion (Table 2). When WP is LOW and the WPEN bit is pro-

grammed HIGH, all Status Register Write Operations are

disabled.

In Circuit Programmable ROM Mode

This mechanism protects the Block Lock and Watchdog

bits from inadvertant corruption. It may be used to per-

form an In Circuit Programmable ROM function by hard-

wiring the WP pin to ground, writing and Block Locking

the desired portion of the array to be ROM, and then pro-

gramming the WPEN bit HIGH.

Read Sequence

When reading from the E2PROM memory array, CS is

ï¬rst pulled low to select the device. The 8-bit READ

instruction is transmitted to the device, followed by the 16-

bit address. After the READ opcode and address are

sent, the data stored in the memory at the selected

address is shifted out on the SO line. The data stored in

memory at the next address can be read sequentially by

continuing to provide clock pulses. The address is auto-

matically incremented to the next higher address after

each byte of data is shifted out. When the highest address

is reached, the address counter rolls over to address

$0000 allowing the read cycle to be continued indeï¬nitely.

The read operation is terminated by taking CS high. Refer

to the Read E2PROM Array Sequence (Figure 1).

To read the Status Register, the CS line is ï¬rst pulled low

to select the device followed by the 8-bit RDSR instruc-

tion. After the RDSR opcode is sent, the contents of the

Status Register are shifted out on the SO line. Refer to

the Read Status Register Sequence (Figure 2).

Write Sequence

Prior to any attempt to write data into the device, the

âWrite Enableâ Latch (WEL) must ï¬rst be set by issuing

the WREN instruction (Figure 3). CS is ï¬rst taken LOW,

then the WREN instruction is clocked into the device.

After all eight bits of the instruction are transmitted, CS

must then be taken HIGH. If the user continues the Write

Operation without taking CS HIGH after issuing the

WREN instruction, the Write Operation will be ignored.

To write data to the E2PROM memory array, the user then

issues the WRITE instruction followed by the 16 bit

address and then the data to be written. Any unused

address bits are speciï¬ed to be â0âsâ. The WRITE opera-

tion minimally takes 32 clocks. CS must go low and

remain low for the duration of the operation. If the address

counter reaches the end of a page and the clock contin-

ues, the counter will roll back to the ï¬rst address of the

page and overwrite any data that may have been previ-

ously written.

Table 2. Block Protect Matrix

STATUS

DEVICE

WEL

WPEN

WP#

BLOCK

PROTECTED

BLOCK

Protected

BLOCK

UNPROTECTED

BLOCK

Protected

Unprotected

STATUS

WPEN, BL0, BL1

WD0, WD1 BITS

Protected

Unprotected

7029 FRM T06

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