X25644 Datasheet, PDF (2/15 Pages) Xicor Inc. – Programmable Watchdog Timer w/Serial E 2 PROM

X25644/46
X25324/26
X25164/66
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present on
the SI pin are latched on the rising edge of the clock input,
while data on the SO pin change after the falling edge of
the clock input.
Chip Select (CS)
When CS is HIGH, the device is deselected and the SO
output pin is at high impedance and unless a nonvolatile
write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device’s, placing it in
the active power mode. It should be noted that after
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Write Protect (WP)
When WP is low and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the device’s Status Register are
disabled, but the part otherwise functions normally. When
WP is held high, all functions, including nonvolatile writes
to the Status Register operate normally. If an internal
Status Register Write Cycle has already been initiated,
WP going low while WPEN is a “1” will have no effect on
this write. Subsequent write attempts to the Status
Register under these conditions will be disabled.
The WP pin function is blocked when the WPEN bit in the
Status Register is “0”. This allows the user to install the
device in a system with WP pin grounded and still be able
to program the Status Register. The WP pin functions will
be enabled when the WPEN bit is set to a “1”.
Reset (RESET/RESET)
RESET/RESET is an active LOW/HIGH, open drain out-
put which goes active whenever the Watchdog Timer is
enabled and CS remains either HIGH or LOW longer than
the selectable Watchdog time-out period. It will remain
active for t_RST, the Reset Timeout period. A falling edge of
CS will reset the Watchdog Timer.
PIN CONFIGURATION
NC
CS
CS
0.345” SO
WP
VSS
NC
14-LEAD SOIC
1
14
2
13
3
12
X25644/46
4
11
5
10
6
9
7
8
0.244”
Not to Scale
NC
V _CC
V _CC
RESET/RESET
SCK
SI
NC
CS
SO
0.197” WP
VSS
8-LEAD SOIC
1
8
2 ^X25324/26 7
X25164/66
3
6
4
5
0.244”
V _CC
RESET/RESET
SCK
SI
14-LEAD TSSOP
CS
SO
NC
0.200” _NC
NC
WP
VSS
1
14
2
13
3 _X25324/28 12
4 ^X25164/66 11
5
10
6
9
7
8
0.177”
V _CC
RESET/RESET
NC
NC
NC
SCK
SI
7036 FRM 02
PIN NAMES
Symbol
Description
CS
Chip Select Input
SO
Serial Output
SI
Serial Input
SCK
Serial Clock Input
WP
V_SS
V_CC
RESET/RESET
Write Protect Input
Ground
Supply Voltage
Reset Output
7029 FRM T01
2