ISL29038 Datasheet, PDF (4/15 Pages) Xicor Inc. – Low Power Ambient Light and Proximity Sensor with Enhanced Infrared Rejection

ISL29038
Electrical Specifications V_DD = 3.0V, T_A = +25°C, R_EXT = 499kΩ 1% tolerance. (Continued)
PARAMETER
DESCRIPTION
CONDITION
DATA_{PROX_F} Full Scale Prox ADC Code
ProxWASH Washout Bit Activation Level
Norwood Solar Emulator
ProxOffsetMax Maximum PROX Offset, Referenced to
Proximity ADC Range
ProxOffsetInc Proximity Offset Adjust Increment Referenced
to Proximity ADC Range
LED DRIVER (IRDR PIN)
t_r
Rise Time for IRDR Sink Current
t_f
Fall time for IRDR Sink Current
I_{IRDR_0} IRDR Sink Current
I_{IRDR_1} IRDR Sink Current
I_{IRDR_2} IRDR Sink Current
I_{IRDR_3} IRDR Sink Current
I_{IRDR_LEAK} IRDR Leakage Current
V_IRDR
IRDR Pin Voltage Compliance
t_PULSE
I_IRDR On Time Per PROX Reading
MISCELLANEOUS
R_LOAD = 15Ω at IRDR pin, 20% to 80%
R_LOAD = 15Ω at IRDR pin, 80% to 20%
PROX_DR = 0; V_IRDR = 0.5V
PROX_DR = 1; V_IRDR = 0.5V
PROX_DR = 2; V_IRDR = 0.5V
PROX_DR = 3; V_IRDR = 0.5V
PROX_EN = 0; V_IRDR = 3.63V
Register bit PROX_DR = 0
V_REF
Voltage of REXT Pin
ALS_EN = 1 or PROX_EN = 1
MIN TYP MAX UNIT
255 Counts
40k
Lux
512 LSB
27
LSB
25
ns
15
ns
31.25
mA
62.5
mA
125
mA
250
mA
0.001 1
µA
0.50
4.3
V
90
µs
0.52
V
I²C Electrical Specifications
For SCL and SDA unless otherwise noted, V_DD = 3V, T_A = +25°C, R_EXT = 499kΩ 1% tolerance (Note 10).
SYMBOL
PARAMETER
TEST CONDITIONS
V_I2C
Supply Voltage Range for I²C Interface
f_SCL
SCL Clock Frequency
V_IL
SCL and SDA Input Low Voltage
V_IH
SCL and SDA Input High Voltage
V_hys
Hysteresis of Schmitt Trigger Input
V_OL
Low-level Output Voltage (open-drain) at 4mA Sink
Current
MIN
1.7
1.25
0.05V_DD
I_i
Input Leakage for each SDA, SCL Pin
-10
t_SP
Pulse Width of Spikes that must be Suppressed by
the Input Filter
t_AA
SCL Falling Edge to SDA Output Data Valid
C_i
Capacitance for each SDA and SCL Pin
t_HD:STA Hold Time START Condition
After this period, the first clock
600
pulse is generated
t_LOW LOW Period of the SCL Clock
Measured at the 30% of VDD
crossing
1300
t_HIGH HIGH period of the SCL Clock
600
t_SU:STA Set-up Time for a START Condition
600
t_HD:DAT Data Hold Time
30
t_SU:DAT Data Set-up Time
100
TYP MAX UNITS
3.63
V
400 kHz
0.55
V
V
V
0.4
V
10
µA
50
ns
900
ns
10
pF
ns
ns
ns
ns
ns
ns
4
FN7851.0
October 12, 2012