X88064 Datasheet, PDF (2/15 Pages) Xicor Inc. – E2 Micro-Peripheral

X88064
Software Data Program Control provides a lower level of
memory write management. SDP controls write opera-
tions to the entire memory. When enabled, the host micro-
processor must send a special 3 byte command sequence
before any byte or page writes to unlocked locations in the
memory.
Pin configuration
DIP/SOIC
NC
A₁₂
NC
NC
WC
PSEN
A/D₀
A/D₁
A/D₂
A/D₃
A/D₄
V_SS
1
24
2
23
3
22
4
21
5
20
6 _X88064 19
7
18
8
17
9
16
10
15
11
14
12
13
V_CC
WR
ALE
A₈
A₉
A₁₁
RD
A₁₀
CE
A/D₇
A/D₆
A/D₅
7023 FRM F02
PIN NAMES
PIN NAME
PSEN
A₈–A₁₂
AD₀–AD₇
WR
RD
WC
CE
ALE
I/O DESCRIPTION
I _{Content of E}² _{memory can be read by lowering the PSEN and holding both RD and WR}
HIGH. The device then places on the data bus (AD₀–AD₇) the contents of E² memory at the
latched address.
I Non-multiplexed high-order Address Bus inputs for the upper byte of the address.
I/O Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a
HIGH to LOW transition.
I During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is
placed on the bus. The rising edge of WR latches data into the device.
I _{The RD input is active LOW and is used to read content of the E}² _{memory at the latched}
address. Both PSEN an WR signals must be held HIGH during RD controlled read operation.
I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order
to disable write to the E² memory. Taking WC HIGH prior to t_BLC (100ns, the time delay from
the last write cycle to the start of internal programming cycle) will inhibit the write operation.
I The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE
HIGH to LOW transition in order to generate a valid internal device select signal. Holding this
pin HIGH and ALE LOW will place the device in standby mode.
I Address Latch Enable input is used to latch the addresses present on the address lines
A₈–A₁₂ and AD₀–AD₇ into the device. The addresses are latched when ALE transitions from
HIGH to LOW.
2