X76F101 Datasheet, PDF (2/17 Pages) Xicor Inc. – Secure SerialFlash

X76F101
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. During
a read cycle, data is shifted out on this pin. During a write
cycle, data is shifted in on this pin. In all other cases, this
pin is in a high impedance state.
Chip Select (CS)
When CS is high, the X76F101 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F101 will be in
standby mode. CS low enables the X76F101, placing it in
the active mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F101 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 7. If at any time during the response to
reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
DEVICE OPERATION
The X76F101 memory array consists of fourteen 8-byte
sectors. Read or write access to the array always begins
at the first address of the sector. Read operations then
can continue indefinitely. Write operations must total 8
bytes.
There are two primary modes of operation for the
X76F101; Protected READ and protected WRITE.
Protected operations must be performed with one of two
8-byte passwords.
The basic method of communication for the device is
established by first enabling the device (CS LOW),
generating a start condition, then transmitting a
command, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
‘0’. The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct
password is accepted and a ACK polling has been
performed, can the data transfer occur.
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
If the X76F101 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to
loading of the command byte. If a stop is issued prior to
the nonvolatile write cycle the write operation will be
terminated and the part will reset and enter into a
standby mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
CS
SDA
SCL
RST
Vcc
Vss
NC
Description
Chip Select Input
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
PIN CONFIGURATION
V_CC
NC
NC
Vss
PDIP
1
8
2
7
3
6
4
5
RST
SCL
SDA
CS
V_SS
CS
SDA
NC
SOIC
1
8
2
7
3
6
4
5
V_CC
RST
SCL
NC
VSS
NC
CS
SDA
MSOP
1
8
2
7
3
6
4
5
VCC
NC
RST
SCL
Smart Card
V_CC
RST
SCL
NC
GND
CS
SDA
NC
2