X68257 Datasheet, PDF (2/14 Pages) Xicor Inc. – E2 Micro-Peripheral

X68257
PIN DESCRIPTIONS
Address/Data (A/D₀–A/D₇)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while AS is HIGH. After AS
transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on R/W, SEL, and
CE.
Addresses (A₈–A₁₄)
High order addresses flow into the device when AS = V_IH
and are latched when AS goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, AS is LOW, and CE
is LOW, the X68257 is placed in the low power standby
mode.
Chip Enable (CE)
Chip Enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
Program Store Enable (SEL)
When the X68257 is to be used in a 68XX-based
system, SEL is tied to V_SS.
Read/Write (R/W)
When the X68257 is to be used in a 68XX-based
system, R/W is tied directly to the microcontroller’s R/W
output.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is HIGH and are latched when AS transitions
from a HIGH to LOW.
PIN NAMES
Symbol
AS
A/D0–A/D7
A₈–A₁₄
E
R/W
CE, CE
SEL
VSS
V_CC
NC
Description
Address Strobe
Address Inputs/Data I/O
Address Inputs
Enable Input
Read/Write Input
Chip Enable
Device Select—Connect to VSS
Ground
Supply Voltage
No Connect
6539 PGM T01.2
PIN CONFIGURATION
A14
A12
AS
SEL
CE
NC
NC
NC
NC
NC
A/D0
A/D1
A/D2
VSS
PDIP
SOIC
1
28
2
27
3
26
4
25
5
24
6
23
7 ^X68257 22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
PLCC
VCC
R/W
A13
A8
A9
A11
E
A10
CE
A/D7
A/D6
A/D5
A/D4
A/D3
6539 FHD F01.3
SEL
CE
NC
NC
NC
NC
NC
NC
A/D0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
X68257
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
A8
A9
A11
NC
E
A10
CE
A/D7
A/D6
6539 FHD F01A.5
2